Optimisation of HEVC motion estimation exploiting SAD and SSD GPU‐based implementation

Khemiri, Randa; Kibeya, Hassan; Sayadi, Fatma Ezahra; Bahri, Nejmeddine; Atri, Mohamed; Nouri, Mohammad

doi:10.1049/iet-ipr.2017.0474

Cited by 22 publications

(18 citation statements)

References 27 publications

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“…The proposed parallel architecture has accelerated the SAD calculation by 3.9Â compared to the serial SAD architecture. In [15], authors have proposed two implementations of the SAD and SSD algorithms using NVIDIA GeForce GTX480 with CUDA language in order to reduce the ME run-time. The proposed architecture saved about 32% of encoding time for class E video sequences with nonsignificant degradation in the PSNR and the bitrate.…”

Section: Related Workmentioning

confidence: 99%

Fast Motion Estimation’s Configuration Using Diamond Pattern and ECU, CFM, and ESD Modes for Reducing HEVC Computational Complexity

Khemiri¹,

Bahri²,

Belghith³

et al. 2020

Digital Imaging

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The high performance of the high efficiency video coding (HEVC) video standard makes it more suitable for high-definition resolutions. Nevertheless, this encoding performance is coupled with a tremendous encoding complexity compared to the earlier H264 video codec. The HEVC complexity is mainly a return to the motion estimation (ME) module that represents the important part of encoding time which makes several researches turn around the optimization of this module. Some works are interested in hardware solutions exploiting the parallel processing of FPGA, GPU, or other multicore architectures, and other works are focused on software optimizations by inducing fast mode decision algorithms. In this context, this article proposes a fast HEVC encoder configuration to speed up the encoding process. The fast configuration uses different options such as the early skip detection (ESD), the early CU termination (ECU), and the coded block flag (CBF) fast method (CFM) modes. Regarding the algorithm of ME, the diamond search (DS) is used in the encoding process through several video resolutions. A time saving around 46.75% is obtained with an acceptable distortion in terms of video quality and bitrate compared to the reference test model HM.16.2. Our contribution is compared to other works for better evaluation.

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Section: Related Workmentioning

confidence: 99%

Fast Motion Estimation’s Configuration Using Diamond Pattern and ECU, CFM, and ESD Modes for Reducing HEVC Computational Complexity

Khemiri¹,

Bahri²,

Belghith³

et al. 2020

Digital Imaging

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“…The research published in [33] proposed an implementation of the ME on a low‐cost NVIDIA GPU. On the basis of principally the SADs or the sum of square differences (SSDs), the authors proposed to accelerate these algorithms.…”

Section: Comparison To the State Of The Artmentioning

confidence: 99%

CUDA memory optimisation strategies for motion estimation

Sayadi

Chouchene

Bahri

et al. 2018

IET Computers & Digital Techniques

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As video processing technologies continue to rise quicker than central processing unit (CPU) performance in complexity and image resolution, data-parallel computing methods will be even more important. In fact, the high-performance, data-parallel architecture of modern graphics processing unit (GPUs) can minimise execution times by orders of magnitude or more. However, creating an optimal GPU implementation not only needs converting sequential implementation of algorithms into parallel ones but, more importantly, needs cautious balancing of the GPU resources. It requires also an understanding of the bottlenecks and defect caused by memory latency and code computing. The defiance is even greater when an implementation exceeds the GPU resources. In this study, the authors discuss the parallelisation and memory optimisation strategies of a computer vision application for motion estimation using the NVIDIA compute unified device architecture (CUDA). It addresses optimisation techniques for algorithms that surpass the GPU resources in either computation or memory resources for CUDA architecture. The proposed implementation reveals a substantial improvement in both speed up (SU) and peak signalto-noise ratio (PSNR). Indeed, the implementation is up to 50 times faster than the CPU counterpart. It also provides an increase in PSNR of the coded test sequence up to 8 dB. 2 Architecture and memory spaces of graphics processing units In the NVIDIA GPU-based architecture, parallelisation is obtained through the execution of tasks in a number of stream processors

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“…To meet the real‐time encoding compliant using embedded systems, researchers have worked on two optimisation aspects: the first aspect focus on algorithmic optimisations [3–6] while the second one represents the software/hardware optimisations using single instruction multiple data set instructions [7, 8] or proposing parallel HEVC implementations [9–12].…”

Section: Introductionmentioning

confidence: 99%