Optimisation of RunBefore decoder and first one detector for MPEG-4 AVC/H.264 CAVLC decoding

Compact hardware architecture for first one detector using priority-based uniform partition

“…circuit area (# of gates) K. Xu [2] 0.18 (MagnaChip) 846 S.J. Lee [3] 756 this work 0.25 (Samsung) 58…”

“…On the other hand, S.J. Lee [3] just announced the comparison data based on the circuit area and the consuming power on the same design technology with the work of [2] without a detailed explanation for the testing environment to evaluate the consuming power such as operating frequency and supply voltage. Therefore, for a fair comparison, we would like to use the gate count to provide an approximate comparison with previous works.…”

“…According to the statistical analysis of the previous works [2,3], the first appearing one in the input bit stream most likely locates in the most significant four bits (d 15 :d 12 ) with the probability of 96%. As shown in the previous section, the FOD output can be simplified effectively, when we evenly divide the input stream into 4 sub-words.…”

“…S.J. Lee [3] applied the non-uniform partition scheme of [2] and suggests the reuse technique of 2-bit priority detector, which can reduce the hardware cost. In this paper, we propose optimized hardware architecture for a FOD.…”