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Digital mobile communication technologies, such as next generation mobile communication and mobile TV, are rapidly advancing. Hardware designs to provide baseband processing of new protocol standards are being actively attempted, because of concurrently emerging multiple standards and diverse needs on device functions, hardwareonly implementation may have reached a limit. To overcome this challenge, digital communication system designs are adopting software solutions that use central processing units or graphics processing units (GPUs) to implement communication protocols. In this article we propose a parallel software implementation of low density parity check decoding algorithms, and we use a multi-core processor and a GPU to achieve both flexibility and high performance. Specifically, we use OpenMP for parallelizing software on a multi-core processor and Compute Unified Device Architecture (CUDA) for parallel software running on a GPU. We process information on H-matrices using OpenMP pragmas on a multi-core processor and execute decoding algorithms in parallel using CUDA on a GPU. We evaluated the performance of the proposed implementation with respect to two different code rates for the China Multimedia Mobile Broadcasting (CMMB) standard, and we verified that the proposed implementation satisfies the CMMB bandwidth requirement.

Owing to advancement in 4 G mobile communication and mobile TV, the throughput requirement in digital communication has been increasing rapidly. Thus, the need for efficient error-correcting codes is increasing. Furthermore, since most mobile devices operate with limited battery power, low-power communication techniques are attracting considerable attention lately. In this article, we propose a novel low-power, low-density parity check (LDPC) decoder. The LDPC code is one of the most common error-correcting codes. In mobile TV, SNR estimation is required for the adaptive coding and modulation technique. We apply the SNR estimation result to the proposed LDPC decoding to minimize power consumption due to unnecessary operations. The SNR estimation value is used for predicting the iteration count until the completion of the successful LDPC decoding. When the SNR value is low, we omit computing the parity check and the tentative decision. We implemented the proposed decoder which is capable of adaptively skipping unnecessary operations based on the SNR estimation. The power consumption was measured to show the efficiency of our approach. We verified that, by using our proposed method, power consumption is reduced by 10% for the SNR range of 1.5-2.5 dB.

No abstract

In this paper, we propose a low-power adaptive low-density parity check (LDPC) decoder that utilizes dynamic voltage and frequency scaling to reduce power consumption. Most existing adaptive LDPC decoders have focused only on the decoding performance based on the signal-to-noise ratio (SNR) estimation. However, significant idle power is consumed when the decoder awaits the next frame after processing a frame. In mobile communication standards such as China Mobile Multimedia Broadcasting and Digital Video Broadcasting Satellite Second Generation, adaptive coding and modulation has been adopted. Thus, it is possible to reduce the power consumption efficiently by using the SNR estimation. In this paper, we apply a customized frequency selection scheme and a variable voltage generation scheme to an adaptive LDPC decoder to reduce the dynamic power consumption. The proposed schemes result in a reduction of 44% in the energy consumption of an LDPC decoder implemented using 0.18-μm complementary metal-oxidesemiconductor technology.