2011
DOI: 10.1186/1687-1499-2011-48
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An adaptive low-power LDPC decoder using SNR estimation

Abstract: Owing to advancement in 4 G mobile communication and mobile TV, the throughput requirement in digital communication has been increasing rapidly. Thus, the need for efficient error-correcting codes is increasing. Furthermore, since most mobile devices operate with limited battery power, low-power communication techniques are attracting considerable attention lately. In this article, we propose a novel low-power, low-density parity check (LDPC) decoder. The LDPC code is one of the most common error-correcting co… Show more

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Cited by 11 publications
(11 citation statements)
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“…However, D_min32 can be said to take small area considering that 32 VN units are required for a 32-parallel LDPC decoder. Moreover, the SNR estimator in a conventional LDPC decoder [10] takes up 12.1% of the total decoder area, the hardware cost of the delta-minima module is relatively low because the proposed algorithm does not need the estimator.…”
Section: Hardware Cost Analysismentioning
confidence: 99%
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“…However, D_min32 can be said to take small area considering that 32 VN units are required for a 32-parallel LDPC decoder. Moreover, the SNR estimator in a conventional LDPC decoder [10] takes up 12.1% of the total decoder area, the hardware cost of the delta-minima module is relatively low because the proposed algorithm does not need the estimator.…”
Section: Hardware Cost Analysismentioning
confidence: 99%
“…Furthermore, even a simple modification of MSA can reduce the loss of the coding gain, so modified versions [6,8] of MSA have been widely adopted in LDPC decoders. Moreover, dynamic approaches of MSA have been discussed in several studies for better performance and throughput [8,10]. In [8], the scaling and offset factors were adjusted adaptively, and [10] utilized a look-up table of the minimum iteration number for adaptive scheduling.…”
Section: Introductionmentioning
confidence: 99%
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“…This new LDPC decoder is based on the adaptive LDPC decoder previously proposed in [16], to which we added a DVFS controller to provide dynamically adjustable operating frequencies and the corresponding supply voltages. To find the optimal operating point for CMMB codes, we carried out various analyses regarding the correlation between the operating frequency and the supply voltage with respect to a certain SNR value.…”
Section: Proposed Low-power Ldpc Decodermentioning
confidence: 99%