Optimization and Implementation of a Viterbi Decoder Under Flexibility Constraints

Abstract

Abstract-This paper discusses the impact of flexibility when designing a Viterbi decoder for both convolutional and TCM codes. Different trade-offs have to be considered in choosing the right architecture for the processing blocks and the resulting hardware penalty is evaluated. We study the impact of symbol quantization that degrades performance and affects the wordlength of the rateflexible trellis datapath. A radix-2-based architecture for this datapath relaxes the hardware requirements on the branch metric and survivor path blocks substantially. The cost of flexibility in terms of cell area and power consumption is explored by an investigation of synthesized designs that provide different transmission rates. Two designs are fabricated in a digital 0.13-m CMOS process. Based on post-layout simulations, a symbol baud rate of 168 Mbaud/s is achieved in TCM mode, equivalent to a maximum throughput of 840 Mbit/s using a 64-QAM constellation.

Viterbi Accelerator for Embedded Processor Datapaths

“…With special considerations at the circuit level, highly optimized fixed-function implementations can be obtained [13]. The circuitry can also include some rudimentary flexibility that allows for reconfiguration between a few operating modes, such as different code rates [14]. Thanks to circuit innovations, despite the 90-nm Viterbi implementation supports several constraint lengths (up to K = 9), it reaches a top performance of almost 2 Gb/s for K = 6 [15].…”

Detector Design and Complexity Analysis for Cooperative Communications in Intersymbol Interference Fading Channels

“…Assuming that receivers can acquire perfect channel knowledge, maximum likelihood sequence estimation (MLSE) can be employed to combat the ISI by searching for the minimum Euclidean distance between observed signal and any given transmitted signals [15]. The Viterbi algorithm [16] is an efficient technique for solving the minimum distance problem, and its implementation has been investigated extensively [17][18][19][20][21]. The traditional Viterbi algorithm as proposed in [16] is directly applicable only to timeinvariant channels.…”

Design and measurement of a variable-rate Viterbi decoder in 130-nm digital CMOS

“…Our flexible Viterbi decoder [9], also belongs to the bandwidthflexible class. It covers a wider range of transmission rates in order to adapt to both low-and high-energy scenarios.…”

“…Design and silicon implementation, together with measurements of the fabricated chip that lead to an overall cost estimation of flexibility, are described in Section 4. A previous evaluation that laid the foundation for the chip [9] solely relied on simulated data. Finally, Section 5 discusses an alternative architecture and evaluates its hardware cost.…”