Optimization of bit-per-stage for low-voltage low-power CMOS pipeline ADCs

Adeniran, O.A.; Demosthenous, Andreas

doi:10.1109/ecctd.2005.1522991

Cited by 8 publications

(3 citation statements)

References 7 publications

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“…Once the first MDAC is calibrated, it is swapped back in place and the process repeated for the 2 nd MDAC, etc. MDAC kT/C-based capacitor scaling [6] can still be used across the pipeline with this scheme to save amplifier power consumption if calibration is limited to the first two MDACs (of the same physical dimension), with the redundant MDAC an exact copy of MDACs 1 and 2 to guarantee thermal noise constraint levels. The calibration concept is described below for the 12-bit ADC implementation.…”

Section: Segmented Analog Calibration Schemementioning

confidence: 99%

“…The use of digital redundancy and digital error correction [2]- [4], simplifies the pipeline ADC design and allows dynamic comparators with large offsets to be employed. Multi-bit internal quantizers are preferred for low-power pipeline ADC designs primarily because inter-stage amplifier count is reduced, with [5] and [6] proposing an optimal partitioning of 2.5-bits-per-stage for lowest power consumption.…”

Section: Introductionmentioning

confidence: 99%

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A Segmented Analog Calibration Scheme for Low-Power Multi-Bit Pipeline ADCs

Adeniran

Demosthenous

2006

2006 13th IEEE International Conference on Electronics, Circuits and Systems

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A segmented background calibration scheme for low-power, high-resolution (>10-bit) multi-bit pipeline analogto-digital converters (ADCs) is described. The technique uses a low-bandwidth, high-precision ∆Σ modulator for MDAC residue digitization, thus negating the need for an ultra-low offset analog comparator. Behavioral simulation results for 1% MDAC capacitor mismatch, show signal-to-noise-plusdistortion ratio (SNDR) improvement of 19 dB and spuriousfree-dynamic-range (SFDR) improvement of 24 dB over an uncalibrated 12-bit ADC. The scheme has small digital and analog silicon area and power consumption overhead, thus making it suitable for low-power video-rate ADCs for mobile applications.

show abstract

Section: Segmented Analog Calibration Schemementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A Segmented Analog Calibration Scheme for Low-Power Multi-Bit Pipeline ADCs

Adeniran

Demosthenous

2006

2006 13th IEEE International Conference on Electronics, Circuits and Systems

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show abstract

“…The total output noise PSD of the DAC is formed from (28), (31), (29), (31) and (32) by solving the v out from (27), replacing v in by the noise source (33) due to resistor R i , and summing the output terms together. Because noise sources do not correlate, the superposition principle applies.…”

Section: Estimation Of the Dac Output Noisementioning

confidence: 99%

An 8-bit, 10 kHz, 5.1 μW, 0.18 μm CMOS SAR ADC for RFID applications with sensing capabilities

Marjonen

Vermesan

Rustad

2010

Analog Integr Circ Sig Process

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An 5.1 lW, 1.8 V, 8-bit, successive approximation (SAR) analog-to-digital converter (ADC) using 10 kHz clock was designed and fabricated in a 0.18 lm CMOS technology for passive UHF radio frequency identification (RFID) applications. The ADC utilises a resistive digital to analog converter (DAC). The ADC can operate with low power consumption. The proposed comparator with cascode active load can offer large gain and can operate at a low supply voltage. The measured total power consumption is 5.1 lW at a 10 kHz input clock with a 1.8 V single supply, and 0.5 lW with 970 mV supply.

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A 94-mW, 100-MS/s, 12-bit pipeline ADC for multi-standard TV demodulation applications

Garcia-Gonzalez¹,

Greitschus²,

Desel³

2009

Analog Integr Circ Sig Process

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This paper presents the design and implementation of a 12-bit Analog-to-Digital Converter (ADC) for multi-standard TV demodulation applications. The ADC was fabricated in a standard digital 90-nm CMOS process and it is built by means of a front-end sample-and-hold and a cascade of 10 pipeline stages with 1.5-bits resolution. Performance of 60-dB signal-to-noise-ratio and 68-dB spurious-free-dynamic-range is obtained without calibration at 100-MS/s with a 1-V P-P input signal swing. The occupied silicon area is 0.5-mm 2 ; and the power consumption of 94-mW from a 1.2-V supply.

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Optimization of bit-per-stage for low-voltage low-power CMOS pipeline ADCs

Cited by 8 publications

References 7 publications

A Segmented Analog Calibration Scheme for Low-Power Multi-Bit Pipeline ADCs

A Segmented Analog Calibration Scheme for Low-Power Multi-Bit Pipeline ADCs

An 8-bit, 10 kHz, 5.1 μW, 0.18 μm CMOS SAR ADC for RFID applications with sensing capabilities

A 94-mW, 100-MS/s, 12-bit pipeline ADC for multi-standard TV demodulation applications

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