Optimization of extrinsic source/drain resistance in ultrathin body double-gate FETs

Abstract

Extrinsic resistance due to contacts and nonabrupt lateral extension doping profile can become a performance-limiter in ultrathin body double-gate FETs (DGFET). In this paper, two-dimensional device simulations are used to study and optimize the extrinsic resistance in a sub-20 nm gate length DGFET. For a given lateral doping gradient, the extension doping needs to be offset from the gate edge by an amount called the underlap. The current drive, and hence transistor performance, is maximized when the underlap is chosen in such a way as to balance the impact of nonabrupt doping on the short channel effects and series resistance. This optimization depends upon the maximum allowed offstate subthreshold leakage current and the electrostatic integrity of the device structure.

Analog and RF performance investigation of cylindrical surrounding-gate MOSFET with an analytical pseudo-2D model

“…In our study, the source/drain contact resistance is calculated considering the optimized source/drain contact resistivity value of 5 µm 2 as given in [46]. It matches well to the ITRS 2009 Edition [1] stipulated value (ρ c < 5 µm 2 ).…”

Effect of gate engineering in double-gate MOSFETs for analog/RF applications

“…Both this R g and R i will introduce additional resistive components, and are added in our simulation to calculate f max . In our simulation study, the source/drain contact resistance is taken as 160 O considering the typical source/drain contact resistivity value of 4 O mm 2 as in [47]. For a scaled device with small gate resistance, other factors like R i , g ds and g m ðC gd =C gs Þpredominates.…”

RF and noise performance of double gate and single gate SOI

“…A typical value for silicide sheet resistance is 2-5 X/sq and a typical value for q con is 20 X lm 2 [35]. In this paper, according [36], for device simulation a lower bound by gate resistance in device scaling is considered using values of R sheet = 2 X/sq and q con = 0. The contact between a metal contact and a thin conducting layer of semiconductor can be described with a resistive network composed by a shunt distributed resistance q c / (W Dy) and the semiconductor distributed series resistance R s0 Dy/W.…”