Optimization of implant anneals to improve transistor performance in a 0.15 μm CMOS technology

Lutze, J.; Miranda, T.; Scott, G.; Olsen, C.; Variam, N.; Mehta, S.

doi:10.1109/55.863108

Cited by 2 publications

(1 citation statement)

References 12 publications

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“…39 Still, some fabrication modules are performed at high temperatures, particularly oxidation for device isolation and gate formation. Fortunately, reduction in thermal budget is already the trend in the microelectronics industry, due to the need to preserve sharp dopant profiles and precise junction depths.…”

Section: Thermal Budget Determinationmentioning

confidence: 99%

Carrier mobilities and process stability of strained Si n- and p-MOSFETs on SiGe virtual substrates

Currie

Leitz

Langdo

et al. 2001

Journal of Vacuum Science &Amp; Technology B: Microelectronics and Nanometer Structures Processing, Measurement, and Phenomena

248

141

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Strained Si n -channel metal-oxide-semiconductor field-effect transistors formed on very thin SiGe relaxed layer fabricated by ion implantation technique Appl. Phys. Lett. 90, 202101 (2007); 10.1063/1.2739324 Asymmetric strain relaxation in patterned SiGe layers: A means to enhance carrier mobilities in Si cap layers Appl. Phys. Lett. 90, 032108 (2007); 10.1063/1.2431702High-quality strain-relaxed SiGe alloy grown on implanted silicon-on-insulator substrate Surface channel strained Si metal-oxide-semiconductor field-effect transistors ͑MOSFETs͒ are a leading contender for future high performance complementary metal-oxide-semiconductor ͑CMOS͒ applications. The carrier mobility enhancement of these devices is studied as a function of channel strain, and the saturation behavior for n-and p-channel devices is compared. Carrier mobility enhancements of up to 1.8 and 1.6 are achieved for n-and p-channel devices, respectively. The process stability of strained Si MOSFETs is also studied, and carrier mobility enhancement is shown to be robust after well implantation and virtual substrate planarization steps. The effects of high-temperature implant activation anneals are also studied. While no misfit dislocation introduction or strain relaxation is observed in these devices, increased interface state densities or alloy scattering due to Ge interdiffusion are shown to decrease mobility enhancements. Channel thickness effects are also examined for strained Si n-MOSFETs. Loss of carrier confinement severely limits the mobility of devices with the thinnest channels. Overall, surface channel strained Si MOSFETs are found to exhibit large carrier mobility enhancements over coprocessed bulk Si devices. This, combined with the high process stability exhibited by these devices, makes them superb candidates for future CMOS applications.

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Section: Thermal Budget Determinationmentioning

confidence: 99%