Optimization of KOH etching process to obtain textured substrates suitable for heterojunction solar cells fabricated by HWCVD

Muñoz, D.; Carreras, P.; Escarré, Jordi; Ibarz, D.; Nicolás, Silvia Martín de; Voz, C.; Asensi, J.M.; Bertomeu, J.

doi:10.1016/j.tsf.2009.01.024

Cited by 59 publications

(28 citation statements)

References 9 publications

Supporting

Mentioning

Contrasting

Unclassified

Order By: Relevance

“…After deposition, the a-Si:H/c-Si stacks were either annealed at 200 C for 5 min or treated in a hydrogen plasma [8,9] depending on the experiment. For the solar cell preparation TCO layers (indium-tin-oxide (ITO), thickness 80 nm) were prepared by DC magnetron sputter deposition on the front and rear side of the previously deposited a-Si:H layers without additional sample heating and by addition of < 1.0 % oxygen to the Ar sputter gas [10]. The actual substrate temperature during deposition remains below 50 °C.…”

Section: Methodsmentioning

confidence: 99%

Evolution of the Charge Carrier Lifetime Characteristics in Crystalline Silicon Wafers During Processing of Heterojunction Solar Cells

et al. 2014

View full text Add to dashboard Cite

Section: Methodsmentioning

confidence: 99%

Evolution of the Charge Carrier Lifetime Characteristics in Crystalline Silicon Wafers During Processing of Heterojunction Solar Cells

et al. 2014

View full text Add to dashboard Cite

“…To further improve the efficiency, the use of textured wafers is necessary. For (100) oriented wafers, this texturization consists in etching anisotropically the wafer to reveal pyramidal structure defined by the {111} planes [4]. These randomly distributed pyramids greatly improve light trapping, and therefore increase the short circuit current density of the solar cells.…”

Section: Introductionmentioning

confidence: 99%

Modification of textured silicon wafer surface morphology for fabrication of heterojunction solar cell with open circuit voltage over 700 mV

Fesquet

Olibet

Damon-Lacoste

et al. 2009

2009 34th IEEE Photovoltaic Specialists Conference (PVSC)

View full text Add to dashboard Cite

Crystalline silicon wafer (c-Si) can be extremely well passivated by plasma enhanced chemical vapor deposited (PECVD) amorphous silicon (a-Si:H) films. As a result, on flat substrates, solar cells with very high open circuit voltage are readily obtained. On textured substrates however the passivation is more cumbersome, likely due to the presence of localized recombinative paths situated at the pyramid valleys. Here, we show that this issue may be resolved by selecting a silicon substrate morphology featuring large pyramids. Chemical post-texturization treatments can further reduce the surface recombination velocity. This sequence has allowed us to fabricate solar cells with open circuit voltage over 700 mV, demonstrating also on device level the effect of pyramid density and surface micro-roughness on the surface passivation quality.

show abstract

“…In present commercial solar cells, 160-200 μm thick cSi wafers are chemically etched in hot potassium hydroxide (KOH) solution to form random pyramids of few to ten microns in size on the wafer surface [3] that reduces the surface reflection by promoting multiple bounces of the incident light. However, such texture with large-scale pyramids is not appropriate for thin wafers due to the high Si consumption during etching and little to no optical diffraction for efficient light-trapping.…”

Section: Introductionmentioning

confidence: 99%

Ultrafast laser direct hard-mask writing for high efficiency c-Si texture designs

et al. 2013

View full text Add to dashboard Cite

This study reports a high-resolution hard-mask laser writing technique to facilitate the selective etching of crystalline silicon (c-Si) into an inverted-pyramidal texture with feature size and periodicity on the order of the wavelength which, thus, provides for both anti-reflection and effective light-trapping of infrared and visible light. The process also enables engineered positional placement of the invertedpyramid thereby providing another parameter for optimal design of an optically efficient pattern. The proposed technique, a non-cleanroom process, is scalable for large area micro-fabrication of high-efficiency thin c-Si photovoltaics. Optical wave simulations suggest the fabricated textured surface with 1.3 μm inverted-pyramids and a single anti-reflective coating increases the relative energy conversion efficiency by 11% compared to the PERL-cell texture with 9 μm inverted pyramids on a 400 μm thick wafer. This efficiency gain is anticipated to improve further for thinner wafers due to enhanced diffractive light trapping effects.

show abstract

Optimization of KOH etching process to obtain textured substrates suitable for heterojunction solar cells fabricated by HWCVD

Abstract: In this work, we have studied the texturization process of (100) c-Si wafers using a low concentration potassium hydroxide solution in order to obtain good quality textured

Cited by 59 publications

References 9 publications

Evolution of the Charge Carrier Lifetime Characteristics in Crystalline Silicon Wafers During Processing of Heterojunction Solar Cells

Evolution of the Charge Carrier Lifetime Characteristics in Crystalline Silicon Wafers During Processing of Heterojunction Solar Cells

Modification of textured silicon wafer surface morphology for fabrication of heterojunction solar cell with open circuit voltage over 700 mV

Ultrafast laser direct hard-mask writing for high efficiency c-Si texture designs

Contact Info

Product

Resources

About