Optimization of Nanoscale Thyristors on SOI for High-Performance High-Density Memories

Yang, Kemeng; Gupta, Roshani; Banna, Srinivasa; Nemati, F.; Cho, H.-J.; Ershov, M.; Tarabbia, M.; Hayes, D.G.; Robins, Scott

doi:10.1109/soi.2006.284460

Cited by 11 publications

(6 citation statements)

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“…Thus, SOI-based compact thyristors using two coupled bipolar transistors triggered by impact ionization are quite temperature-sensitive and require precise doping control in the channel to obtain stable performance. 29 The FB-FET, utilizing the feedback between carrier flows and their injection barriers, does not use impact ionization or channel doping, but suffers from the poor controllability of the surface charge that forms the injection barriers. The FED, though using two front gates instead of surface charge for better controllability, faces challenges in fabricating two adjacent front gates.…”

Section: A Feedback-based High-current Sharp-switching Device: Z 2 -Fetmentioning

confidence: 99%

Sharp‐Switching CMOS‐Compatible Devices with High Current Drive

Wan¹,

Cristoloveanu²,

Le³

et al. 2013

Future Trends in Microelectronics

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Section: A Feedback-based High-current Sharp-switching Device: Z 2 -Fetmentioning

confidence: 99%

Sharp‐Switching CMOS‐Compatible Devices with High Current Drive

Wan¹,

Cristoloveanu²,

Le³

et al. 2013

Future Trends in Microelectronics

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show abstract

“…To achieve low voltage operation, thin capacitively coupled thyristor (TCCT) was proposed. [17][18][19] The TCCT has the gated thyristor structure, and excess carriers are transferred from the P + region (anode) through the potential barrier which is induced by the built-in potential between p-n junctions located at anode. While TCCT shows fast and low voltage operation, accurate control of doping profile is needed for stable characteristics.…”

Section: Introductionmentioning

confidence: 99%

Excellent scalability including self-heating phenomena of vertical-channel field-effect-diode type capacitor-less one transistor dynamic random access memory cell

Imamoto

Endoh

2014

Jpn. J. Appl. Phys.

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The scalability study and the impact of the self-heating effect (SHE) on memory operation of the bulk vertical-channel field effect diode (FED) type capacitorless one transistor (1T) dynamic random access memory (DRAM) cell are investigated via device simulator for the first time. The vertical-channel FED type 1T-DRAM cell shows the excellent hold characteristics (100 ms at 358 K of ambient temperature) with large enough read current margin (1 µA/cell) even when silicon pillar diameter (D) is scaled down from 20 to 12 nm. It is also shown that by employing the vertical-channel FED type, maximum lattice temperature in the memory cell due to SHE ( ) can be suppressed to a negligible small value and only reach 300.6 from 300 K ambient temperature due to the low lateral electric field, while the vertical-channel bipolar junction transistor (BJT) type 1T-DRAM shows significant SHE ( K). Moreover, this excellent thermal characteristic can be maintained even when D is scaled down from 20 to 12 nm.

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“…To achieve low voltage operation, thin capacitivelycoupled thyristor (TCCT) was proposed. [15][16][17] The TCCT has the gated thyristor structure, and excess majority carriers are transferred from the P þ region through the potential barrier induced by the N þ region. While TCCT shows fast and low voltage operation, accurate control of doping profile is needed for stable characteristics.…”

Section: Introductionmentioning

confidence: 99%

“…While TCCT shows fast and low voltage operation, accurate control of doping profile is needed for stable characteristics. 16) Recently, the field effect diode (FED) type 1T-DRAM cell was proposed. [18][19][20] In the FED type 1T-DRAM cell, the potential barrier is controlled by the gate bias instead of the doping profile.…”

Section: Introductionmentioning

confidence: 99%

Novel Field Effect Diode Type Vertical Capacitorless One Transistor Dynamic Random Access Memory Cell with Negative Hold Bit Line Bias Scheme for Improving the Hold Characteristics

Imamoto

Endoh

2013

Jpn. J. Appl. Phys.

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In this paper, the novel field effect diode (FED) type vertical capacitorless one transistor dynamic random access memory (1T-DRAM) cell with negative hold bit line (BL) voltage (V BL) scheme is proposed. In comparison with the conventional planar type, the proposed vertical type with negative hold V BL scheme shows excellent static and disturb retention time. The proposed vertical type memory cell with negative hold V BL scheme achieves 1,000 times longer static retention time and 104 times longer BL disturb retention time at 85 °C than that of the conventional planar type. Furthermore, the proposed vertical type memory cell has a small cell size of 4F2 due to its stacked vertical structure. The proposed FED type vertical capacitorless 1T-DRAM cell with negative hold V BL scheme is shown to be an excellent candidate for stand-alone and embedded memory applications and extends scaling limitations.

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Optimization of Nanoscale Thyristors on SOI for High-Performance High-Density Memories

Cited by 11 publications

References 0 publications

Sharp‐Switching CMOS‐Compatible Devices with High Current Drive

Sharp‐Switching CMOS‐Compatible Devices with High Current Drive

Excellent scalability including self-heating phenomena of vertical-channel field-effect-diode type capacitor-less one transistor dynamic random access memory cell

Novel Field Effect Diode Type Vertical Capacitorless One Transistor Dynamic Random Access Memory Cell with Negative Hold Bit Line Bias Scheme for Improving the Hold Characteristics

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