Optimization of Parallel Discrete Event Simulator for Multi-core Systems

Abstract

Abstract-Parallel Discrete Event Simulation (PDES) can substantially improve performance and capacity of simulation, allowing the study of larger, more detailed models, in shorter times. PDES is a fine-grained parallel application whose performance and scalability are limited by communication latencies. Traditionally, PDES simulation kernels use processes that communicate using message passing; shared memory is used to optimize message passing for processes running on the same machine. We report on our experiences in implementing a thread-based version of the ROSS simulator. The multithreaded implementation eliminates multiple message copying and significantly minimizes synchronization delays. We study the performance of the simulator on two hardware platforms: a Core i7 machine and a 48-core AMD Opteron Magny-Cours system. We identify performance bottlenecks and propose and evaluate mechanisms to overcome them. Results show that multithreaded implementation improves performance over the MPI version by up to a factor of 3 for the Core i7 machine and 1.2 on Magny-cours for 48-way simulation.

Characterizing and Understanding PDES Behavior on Tilera Architecture

“…Recently, continuing emergence of multicore processors and the potential of these architectures to drastically minimize the impact of communication-related issues motivated several studies that examine performance and scalability of PDES in these environments [1], [2]. For example, the work of [2] demonstrated the advantages of using multithreaded (as opposed to multiprocess) implementation of ROSS simulator [3] on a quad-core Intel Core i7 machine and on a AMD Magny-cours system [4] composed of four 12-core chips for the total of 48 cores. Several optimizations were also proposed that allowed almost 3x performance improvement for the multithreaded version over baseline MPI-based implementation of ROSS [2].…”

“…For example, the work of [2] demonstrated the advantages of using multithreaded (as opposed to multiprocess) implementation of ROSS simulator [3] on a quad-core Intel Core i7 machine and on a AMD Magny-cours system [4] composed of four 12-core chips for the total of 48 cores. Several optimizations were also proposed that allowed almost 3x performance improvement for the multithreaded version over baseline MPI-based implementation of ROSS [2].…”

“…The starting point of our exploration of PDES behavior on the Tilera platform is the multithreaded implementation of ROSS simulator [3] that was developed in a recent work [2]. Multithreaded PDES directly exploits the presence of shared levels of memory hierarchy on the chip (the shared L2 cache in the case of the Tilera) and eliminates delays due to multiple message copying operations and synchronization delays involved in polling of the queues that are inherent in MPI-based implementations.…”

“…Multithreaded PDES directly exploits the presence of shared levels of memory hierarchy on the chip (the shared L2 cache in the case of the Tilera) and eliminates delays due to multiple message copying operations and synchronization delays involved in polling of the queues that are inherent in MPI-based implementations. The work of [2] showed that multithreaded implementation significantly outperforms the MPI-based design on platforms such as Intel Core i7 and AMD Magny-cours. In this paper, we demonstrate that a multithreaded simulator also significantly outperforms the MPI-based version on the Tilera, especially when a number of performance optimizations are introduced.…”

“…In terms of performance optimizations, we propose to adapt three techniques introduced in [2] such that they exploit the features of the Tilera. We also propose some new optimizations that utilize the APIs available from the Tilera Multicore Components (TMC) library; more details on these are provided in Section 3.…”