Optimization of periphery circuits in a 1K-bit PCRAM chip for highly reliable write and read operations

Abstract

A 1K-bit phase change random access memory (PCRAM) with improved periphery circuits for better reliable operations has been successfully developed in 130 nm CMOS technology. A flexible write driver is proposed to provide a novel continuous step-down pulses by studying programming strategies while a reliable read circuit is designed by investigating the special transition characteristics of PCRAM, leading to an effective write operation and a non-destructive read operation without any additional changes of the storage states. In addition, a large sense margin has been achieved and the read results corresponding well with the write operations, which demonstrate the influences of technology variations have been considerably decreased with the proposed periphery circuits.

Methods to speed up read operation in a 64 Mbit phase change memory chip

“…The simulated sense time of our SA is 42 ns. The difference between this SA and the one we described in another literature [9], is that, we propose a bias voltage V b to replace the reference resistor branch. Since there are 384 SAs shared one group of V b and V c generators in the chip, this method could reduce the total area of SAs.…”

Near-threshold SIDO DC-DC converter with a high-precision ZCD for phase change memory chip

“…Flash memory can only work in block manipulation. Comparing with traditional nonvolatile memory, PCRAM can be changed resistance to store data by different current, so it can be operated bit-by-bit and reduce power consumption in wireless senor network [13,14]. In PCRAM chips, write operation needs high power voltage to ensure success, and read and logic operation use low power voltage to reduce power consumption.…”