Optimization Techniques for ADL-Driven RTL Processor Synthesis

Schliebusch, Oliver; Chattopadhyay, Anupam; Witte, Ernst Martin; Kammler, David W.; Ascheid, Gerd; Leupers, Rainer; Meyr, H.

doi:10.1109/rsp.2005.36

Cited by 15 publications

(21 citation statements)

References 20 publications

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“…However, there are two main drawbacks of ADL-based methods. (i) The limitations of the above mentioned target architecture models may inhibit the designer to accurately optimize the design [18][19][20][21] and (ii) they have a very limited scope, since only storedprogram microprocessors can be described with them [22,23].…”

Section: Methods For Optimized Architectural Designmentioning

confidence: 99%

Semi-Automatic RTL Methods for System-on-Chip IP Delivery in the Cyber-Physical System Era

Horváth

Hosszú

Kovács

2016

Period. Polytech. Elec. Eng. Comp. Sci.

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With the dawn of Cyber-Physical Systems (CPS) the relevance of System-on-Chips equipped with run-time configurable, application-specific macrocells increases as numerous tasks has to be taken over from the microprocessors in order to Keywords ARTL, AMDL, CPS, SoC, microarchitecture, RTL design IntroductionIn the recent decade the most spectacular change in the field of digital system design has been the rise of the design entry's abstraction level and the usage of automated methods in the early stages of the design process. This is caused by the ever-increasing time-to-market and time-on-market pressure which has become one of the most important design objectives nowadays. With the dawn of the Cyber-Physical Systems (CPS) integrating physical processes and computation systems directly influencing each other via feedback loops, a huge amount of possible applications emerged and, since the development platforms and tools are very efficient and widely known, the development time has become the key factor on the common market [1,2,3].Because of these characteristics of the backend application requirements, the central data processing hardware components of these systems [4, 5] mainly comprise pre-designed, optimized, and pre-verified macrocells and the focus of digital design shifted to the high level methods used for integrating these components into functionally complete, intelligent systems [6][7][8][9].The foresaid demand for a fast development process in the application area implicitly places major demands upon the computation capacities of the underlying SoCs as well: The intelligence of the CPS applications is usually provided by the software environment running on an embedded microprocessor. These software applications tend to be more and more complex, therefore, the significance of the operating systembased runtime environments is also increasing, even in small designs. Similarly to the hardware development, the tool chains of the application software products are also based on the increasing abstraction (interpreted scripting languages, virtual machines etc.) requiring microprocessors with impressive computation capacities. Moreover, CPS applications are typically real-time systems necessitating predictable computation delays. This predictability is mainly handled by outsourcing the timing-critical tasks to application-specific, highly configurable Intellectual Property (IP) cores instead of performing them in software running on an Instruction-Set Processor (ISP) [10][11][12][13]. Since the overall characteristics of SoCs, such

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Section: Methods For Optimized Architectural Designmentioning

confidence: 99%

Semi-Automatic RTL Methods for System-on-Chip IP Delivery in the Cyber-Physical System Era

Horváth

Hosszú

Kovács

2016

Period. Polytech. Elec. Eng. Comp. Sci.

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“…The design frameworks based on ADLs place great emphasis on instruction set simulation and other software components (compiler, assembler, and debugger generation) [24][25][26] rather than the automated hardware generation [27,28]. In case of ADL-based design frameworks whose aim is to generate a hardware model from the ADL specification, the designer often has to deal with significant restrictions in terms of microarchitecture [29][30][31] (e.g. singleissue pipeline, VLIW, implicit instruction pointer, and interrupt handling mechanism), and they often compromise or neglect the quality of the final ASIP implementation.…”

Section: Algorithmic Modeling Of Asipsmentioning

confidence: 99%

“…This latter solution necessitates additional knowledge in RTL microprocessor development. Furthermore, ADLs are not able to model application-specific data processors with dedicated functionality [4,30].…”

Section: Algorithmic Modeling Of Asipsmentioning

confidence: 99%

A proposed synthesis method for Application-Specific Instruction Set Processors

Horváth

Hosszú

Kovács

2015

Microelectronics Journal

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a b s t r a c tDue to the rapid technology advancement in integrated circuit era, the need for the high computation performance together with increasing complexity and manufacturing costs has raised the demand for high-performance configurable designs; therefore, the Application-Specific Instruction Set Processors (ASIPs) are widely used in SoC design. The automated generation of software tools for ASIPs is a commonly used technique, but the automated hardware model generation is less frequently applied in terms of final RTL implementations. Contrary to this, the final register-transfer level models are usually created, at least partly, manually. This paper presents a novel approach for automated hardware model generation for ASIPs. The new solution is based on a novel abstract ASIP model and a modeling language (Algorithmic Microarchitecture Description Language, AMDL) optimized for this architecture model. The proposed AMDL-based pre-synthesis method is based on a set of pre-defined VHDL implementation schemes, which ensure the qualities of the automatically generated register-transfer level models in terms of resource requirement and operation frequency. The design framework implementing the algorithms required by the synthesis method is also presented.

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“…While optimizing a processor implementation from highlevel specification is a well-researched topic [112][113][114], specific optimizations for reconfigurable processors are rarely proposed. In a recent work, reconfigurability is used for dynamically power gating the architecture to deliver increased energy efficiency [115].…”

Section: Architecture Customizabilitymentioning

confidence: 99%

Ingredients of Adaptability: A Survey of Reconfigurable Processors

Chattopadhyay

2013

VLSI Design

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For a design to survive unforeseen physical effects like aging, temperature variation, and/or emergence of new application standards, adaptability needs to be supported. Adaptability, in its complete strength, is present in reconfigurable processors, which makes it an important IP in modern System-on-Chips (SoCs). Reconfigurable processors have risen to prominence as a dominant computing platform across embedded, general-purpose, and high-performance application domains during the last decade. Significant advances have been made in many areas such as, identifying the advantages of reconfigurable platforms, their modeling, implementation flow and finally towards early commercial acceptance. This paper reviews these progresses from various perspectives with particular emphasis on fundamental challenges and their solutions. Empowered with the analysis of past, the future research roadmap is proposed.

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Optimization Techniques for ADL-Driven RTL Processor Synthesis

Cited by 15 publications

References 20 publications

Semi-Automatic RTL Methods for System-on-Chip IP Delivery in the Cyber-Physical System Era

Semi-Automatic RTL Methods for System-on-Chip IP Delivery in the Cyber-Physical System Era

A proposed synthesis method for Application-Specific Instruction Set Processors

Ingredients of Adaptability: A Survey of Reconfigurable Processors

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