Optimized ASIC/FPGA design flow for energy efficient network nodes

Abstract

This paper describes the ENERSAVE research project, which is funded by the German ministry of research. The project target is a 30 percent power reduction for network nodes via introduction of a holistic, energy‐aware design flow for application‐specific integrated circuit (ASIC) and field programmable gate array (FPGA) design. Using today's state of the art design methods, advanced calculation of system power budgets is a major challenge since current methods do not offer sufficient means for supporting energy awareness and efficiency throughout the complete component design process. The ENERSAVE project is developing a methodology to support power awareness and provides the ability to target power constraints from the system level all the way down to the silicon. It introduces formal tools for power optimizations and demonstrates, on an optical transmission system card, how using this new design methodology enables the envisioned power target to be achieved. The paper presents methodology improvement results to date and offers a preview of expected demonstrable results by project completion in 2014. © 2013 Alcatel‐Lucent.

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