Optimized Gate Diffusion Input Method-Based Reversible Magnitude Arithmetic Unit Using Non-dominated Sorting Genetic Algorithm II

Abiri, Ebrahim; Darabi, Abdolreza; Salehi, Mohammad Reza; Sadeghi, Ayoub

doi:10.1007/s00034-020-01382-1

Cited by 20 publications

(14 citation statements)

References 28 publications

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“…3 The CNTFET technology specifications include ballistic transport, low OFF-current, high speed, low power, and controllable threshold voltage (V th ). As a perfect advantage for the chip area, the N-CNTFET and P-CNTFET can scale down identical, 4 whereas in the MOSFET technology, usually the sizes of the PMOS transistors are considered bigger than the NMOS types. Figure 1 shows the N-CNTFET structure, 5 in which carbon nanotubes (CNTs) graphene sheets wrapped into the tubes and circumference of the nanotubes is expressed by chirality vector of (1).…”

Section: Introductionmentioning

confidence: 99%

SR‐GDI CNTFET‐based magnitude comparator for new generation of programmable integrated circuits

Shiri

Sadeghi

Rafiee

et al. 2022

Circuit Theory & Apps

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Summary The performance of the programmable integrated circuits (ICs) like digital signal processors (DSPs), central processing units (CPUs), and microcontrollers is highly dependent on the magnitude comparators. This article presents a new reliable and efficient 1‐bit comparator based on carbon nanotube field‐effect transistors (CNTFETs) technology. The gate diffusion input (GDI) technique is used to reduce the number of transistors. Also, single swing restoration (SR) transistors and transmission gate (TG) techniques are combined to attain full‐swing outputs with high driving capability. The low internal capacitances and the fewer number of internal nodes of the proposed comparator make it low‐power both in single‐bit and multibit (2‐bit, 4‐bit, 8‐bit, and 16‐bit) implementations. Variations analyses of the circuit and technology parameters are performed that show the cell efficiency. From the layout results, the 1‐bit and 16‐bit comparators occupy 0.1944 μm2 and 37.485 μm2 as the total die area, respectively. The proposed circuit is implemented in image processing in which the best performance compared with state‐of‐the‐art designs regarding hardware complexity, circuitry performance, and image quality assessments are confirmed, by at least 50% improvements of different critical parameters. The resulted figure of merits nominates the cell for future ICs.

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Section: Introductionmentioning

confidence: 99%

SR‐GDI CNTFET‐based magnitude comparator for new generation of programmable integrated circuits

Shiri

Sadeghi

Rafiee

et al. 2022

Circuit Theory & Apps

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“…erefore, the problem of low diagnosis accuracy can be solved by adjusting random parameters through optimization algorithms and iteratively searching for the optimal parameters of the model. ere are several common optimization algorithms, such as simulated annealing algorithm [22], genetic algorithm [23], Bayesian algorithm [24], and particle swarm algorithm [25]. Particle swarm optimization (PSO) algorithm is more popular in the past few years.…”

Section: Introductionmentioning

confidence: 99%

An Intelligent Fault Diagnosis Method for Transformer Based on IPSO-gcForest

Liu

Luo

et al. 2021

Mathematical Problems in Engineering

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Transformers are the main equipment for power system operation. Undiagnosed faults in the internal components of the transformer will increase the downtime during operation and cause significant economic losses. Efficient and accurate transformer fault diagnosis is an important part of power grid research, which plays a key role in the safe and stable operation of the power system. Existing traditional transformer fault diagnosis methods have the problems of low accuracy, difficulty in effectively processing fault characteristic information, and superparameters that adversely affect transformer fault diagnosis. In this paper, we propose a transformer fault diagnosis method based on improved particle swarm optimization (IPSO) and multigrained cascade forest (gcForest). Considering the correlation between the characteristic gas dissolved in oil and the type of fault, firstly, the noncode ratios of the characteristic gas dissolved in the oil are determined as the characteristic parameter of the model. Then, the IPSO algorithm is used to iteratively optimize the parameters of the gcForest model and obtain the optimal parameters with the highest diagnostic accuracy. Finally, the diagnosis effect of IPSO-gcForest model under different characteristic parameters and size samples is analyzed by identification experiments and compared with that of various methods. The results show that the diagnostic effect of the model with noncode ratios as the characteristic parameter is better than DGA data, IEC ratios, and Rogers ratios. And the IPSO-gcForest model can effectively improve the accuracy of transformer fault diagnosis, thus verifying the feasibility and effectiveness of the method.

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“…Also, the gate-diffusion input (GDI) method is a logic design methodology for reducing power consumption, propagation delay under PVT corners, enhanced hazard tolerance and maintaining low area complexity in digital combinatorial circuits [10]. Until now, CNT-MOSFET technology-based modified GDI (m-GDI) has been used in designing energy-efficient circuits [11]. In the present paper, GAA CNT-MOSFET-based GDI method (GAA CNT-GDI) with no bulk terminal and all body effects compared with its common CNT-MOSFET-based design counterpart [10], with high compatible and immunity against misaligned/mis-positioned challenges of CNT transistors technology in fabrication phase is introduced for memory bit-cell array design.…”

Section: Introductionmentioning

confidence: 99%

“…Fig 11. The proposed general block diagram for facile evaluation and estimation of the V DR parameter.…”

mentioning

confidence: 99%

A wrap-gate CNT-MOSFET based SRAM bit-cell with asymmetrical ground gating and built-in read-assist schemes for limited-energy environments application

Darabi

Salehi

Abiri

2021

Preprint

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Today, designing low-power single-bit SRAM structures with the ability to operate regularly at low supply voltages and with high immunity against standard radiation particles impact is challenging for designers. In the present article, a novel design of a low-power radiation-hardened single-ended SRAM bit-cell (UPRHSE) based on gate-diffusion input (GDI) method using gate-all-around carbon nano-tube (CNT) MOSFETs (GAA CNT-MOSFETs) along with dual-chirality/multiple-diameter technique for CNTs with an asymmetric virtual ground gating and built-in read-assist schemes with inherent single-node event upset (SEU) preventive and self-correction capabilities and a high degree of robustness against multiple-node event upsets (MEUs) in the presence of more consumption area storage has been proposed. In order to investigate single/double upset injection circuit model using the structure of the T-connected pseudo resistors (TPRs) has been proposed. Also, based on the analytical-compact model, an equation for calculating the data-retention voltage (VDR) metric for the suggested bit-cell structure and an algorithm for facile estimate of VDR for other bit-cell architectures is presented. The results of extensive Monte-Carlo (MC) simulations to evaluate the proposed bit-cell indicate larger noise margins, acceptable yield, less sensitivity to process, voltage and temperature (PVT) variations, higher critical charge and consequence more robustness to soft errors with high reliability of data storage in standby mode in the presence of voltage conditions lower than the nominal power supply, and better results in other comprehensive figure of merits (FoMs) criteria compared to nanotechnology-based state-of-the-art radiation-hardened (rad-hard) bit-cell circuits with the same number of transistors in the 16 nm technology node. So, the proposed UPRHSE design can be a reasonable choice for applications that demands high stability, impact resistance to radiation particles and extremely low power in a radiation abundant environment with limited-energy sources. Finally, in order to use the suggested UPRHSE bit-cell in a real application with secure data transfer approach, the suggested structure is employed for storing. The results show the better performance of UPRHSE in terms of other comprehensive FoMs based on PSNR and MSSIM metric to evaluate the appropriate accuracy in pixel-by-pixel image compared to other well-known counterpart designs.

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Optimized Gate Diffusion Input Method-Based Reversible Magnitude Arithmetic Unit Using Non-dominated Sorting Genetic Algorithm II

Cited by 20 publications

References 28 publications

SR‐GDI CNTFET‐based magnitude comparator for new generation of programmable integrated circuits

SR‐GDI CNTFET‐based magnitude comparator for new generation of programmable integrated circuits

An Intelligent Fault Diagnosis Method for Transformer Based on IPSO-gcForest

A wrap-gate CNT-MOSFET based SRAM bit-cell with asymmetrical ground gating and built-in read-assist schemes for limited-energy environments application

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