Optimized Polynomial Multiplier Over Commutative Rings on FPGAs: A Case Study on BIKE

Hu, Jingwei; Wang, Wen; Cheung, Ray C. C.; Wang, Huaxiong

doi:10.1109/icfpt47387.2019.00035

Cited by 10 publications

(7 citation statements)

References 8 publications

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“…In this section, we present the hardware design of the sparse polynomial multiplier for BIKE. In 2019, Hu et al [HWCW19] already applied the approach of sparse multiplications to BIKE. However, compared to their design, our optimized implementation achieves a better area-time product and reduces the latency (for detailed information see Section 4.2).…”

Section: Sparse Polynomial Multipliermentioning

confidence: 99%

“…Hence, it can be used for all multiplications required in BIKE. Additionally, the design performs the encoding [HWCW19]. Since the authors of [RBMG21] only reported implementation results for r = 10 163, we extracted the multiplier from their code and synthesized it for r = 12 323.…”

Section: Multipliermentioning

confidence: 99%

“…Compared to the multiplier from [HWCW19], our design achieves a considerably lower latency albeit our results were generated for a larger parameter set. Our design mainly differentiates from their implementation in two parts.…”

Section: Multipliermentioning

confidence: 99%

“…However, we decided not to use this option but rather instantiate two memories since it is a more generic approach which is universally applicable to other hardware devices as well. Second, our rotation unit performs the whole rotation within one clock cycle while the design by [HWCW19] requires log b clock cycles. Even though our multiplier architectures consume slightly more slices, it clearly improves the AT product.…”

Section: Multipliermentioning

confidence: 99%

“…In further detail, BIKE poses several challenges on the arithmetic level. For improving the polynomial multipliers in code-based schemes, Hu et al [HWCW19] presented two different approaches. While the first design is based on a schoolbook multiplication, the second multiplier improves multiplications by exploiting the sparseness of the polynomials used in QC-MDPC codes.…”

Section: Introductionmentioning

confidence: 99%

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Racing BIKE: Improved Polynomial Multiplication and Inversion in Hardware

Richter-Brockmann

Chen

Ghosh

et al. 2021

TCHES

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BIKE is a Key Encapsulation Mechanism selected as an alternate candidate in NIST’s PQC standardization process, in which performance plays a significant role in the third round. This paper presents FPGA implementations of BIKE with the best area-time performance reported in literature. We optimize two key arithmetic operations, which are the sparse polynomial multiplication and the polynomial inversion. Our sparse multiplier achieves time-constancy for sparse polynomials of indefinite Hamming weight used in BIKE’s encapsulation. The polynomial inversion is based on the extended Euclidean algorithm, which is unprecedented in current BIKE implementations. Our optimized design results in a 5.5 times faster key generation compared to previous implementations based on Fermat’s little theorem.Besides the arithmetic optimizations, we present a united hardware design of BIKE with shared resources and shared sub-modules among KEM functionalities. On Xilinx Artix-7 FPGAs, our light-weight implementation consumes only 3 777 slices and performs a key generation, encapsulation, and decapsulation in 3 797 μs, 443 μs, and 6 896 μs, respectively. Our high-speed design requires 7 332 slices and performs the three KEM operations in 1 672 μs, 132 μs, and 1 892 μs, respectively.

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Section: Sparse Polynomial Multipliermentioning

confidence: 99%

Section: Multipliermentioning

confidence: 99%

Section: Multipliermentioning

confidence: 99%

Section: Multipliermentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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