Optimized power combining technique to design a 20dB gain, 13.5dBm OCP1 60GHz power amplifier using 65nm CMOS technology

Aloui, Sofiane; Luque, Yohann; Demirel, Nejdat; Leite, Bernardo; Plana, R.; Belot, Didier; Kerhervé, Eric

doi:10.1109/rfic.2012.6242230

Cited by 5 publications

(4 citation statements)

References 9 publications

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“…As in advanced technology passive devices remain relatively the same size, the power combiner size is normally dominated by the passive elements. Higher OP 1 dB thereby does not necessarily lead to a higher power density since the latter is strongly associated with not only the combining efficiency provided by the combining network, but also the area of the power distribution network [8,9]. For example, Wilkinson power combiner [10] requires l/4 T-line that occupies a large area with high loss and hence severely degrades power combining efficiency, defined as output power divided by area.…”

Section: Introductionmentioning

confidence: 99%

Complementary metal–oxide–semiconductor 60 GHz power amplifier by in‐phase power combining and digitally assisted power back‐off efficiency enhancement

Yu²,

Liang³

et al. 2016

IET Microwaves, Antennas & Propagation

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A two‐dimensional in‐phase power combining with digitally assisted self‐tuning is demonstrated in this study for complementary metal–oxide–semiconductor (CMOS) 60 GHz power amplifier (PA) to improve power efficiency. One digitally assisted 4‐way power‐combined PA prototype was implemented in 65‐nm CMOS process. The performance of measured results show output power of 17.2 dBm, power added efficiency of 11.3% with 1.2 V supply voltage, and up to 170–190% efficiency improvement during power back‐off for the entire 7 GHz band at 60 GHz.

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Section: Introductionmentioning

confidence: 99%

Complementary metal–oxide–semiconductor 60 GHz power amplifier by in‐phase power combining and digitally assisted power back‐off efficiency enhancement

Yu²,

Liang³

et al. 2016

IET Microwaves, Antennas & Propagation

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“…Moreover, these structures perform balanced-to-unbalanced mode conversion. Mixed voltage and current combiners [7][8] represent a good tradeoff to improve effectively the output power.…”

Section: Introductionmentioning

confidence: 99%

A 1.2V 20 dBm 60 GHz power amplifier with 32.4 dB Gain and 20 % Peak PAE in 65nm CMOS

Larie¹,

Kerhervé²,

Martineau³

et al. 2014

ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)

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A 60 GHz highly linear Power Amplifier (PA) is implemented in 65-nm Low Power (LP) CMOS technology. The structure consists of four common-source pseudo-differential stages. To improve global performances, a compact transformerbased 8-way power combiner is designed. Three driver stages are neutralized with capacitors to enhance both reverse isolation and power gain. At 60 GHz, the PA delivers a saturated output power (P SAT ) of 19.9 dBm and a 1-dB compressed output power (P -1dB ) of 17.2 dBm while achieving maximum power added efficiency (PAE max ) of 20 %. The small-signal gain is about 33 dB with a 3-dB bandwidth of 9 GHz. The circuit occupies an active area of 0.32 mm². To the author's knowledge, this amplifier presents the highest figure of merit (FoM ITRS) among 60 GHz PAs using silicon technology.

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“…Passive power combining can be utilized, provided its insertion loss is less than the PA added power. Techniques to efficiently combine power from two or more PA cells on‐chip have been reported in . In , an eight‐way power combiner (8WPC) was designed using microstrip lines with 1.1 dB/mm loss at 60 GHz.…”

Section: Introductionmentioning

confidence: 99%

“…This combiner provided zero‐degree phase translation and is only suitable for integration with single‐ended PA topology. Conversely, the two‐WPC (2WPC) described in are suitable for differential topology which itself offers a number of advantages over the single‐ended type. These advantages include excellent noise immunity due to inherently high common‐mode rejection (CMR) ratio, significantly low even‐order harmonic signal levels, and insensitivity to parasitic inductance between common emitter/source connection and ground.…”

Section: Introductionmentioning

confidence: 99%

E-band transformer-based differential 4-way power-combining amplifier

Thian

2014

Microw. Opt. Technol. Lett.

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This paper presents the design and implementation of a differential 4-way powercombining amplifier operating at E-band. The proposed 4-way power combiner (4WPC) facilitates short interconnects to the PA cells, thereby resulting in reduced loss. Simple C-L-C and L-C networks are deployed in order to compensate inductive loading due to the routing lines that would otherwise introduce mismatch and subsequently increase overall loss. Realized in SiGe technology, the PA prototype delivered 13.2 dBm output-referred 1-dB compression point and 14.3 dBm saturated output power when operated from a single 3.3 V DC supply at 75 GHz.

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Optimized power combining technique to design a 20dB gain, 13.5dBm OCP1 60GHz power amplifier using 65nm CMOS technology

Cited by 5 publications

References 9 publications

Complementary metal–oxide–semiconductor 60 GHz power amplifier by in‐phase power combining and digitally assisted power back‐off efficiency enhancement

Complementary metal–oxide–semiconductor 60 GHz power amplifier by in‐phase power combining and digitally assisted power back‐off efficiency enhancement

A 1.2V 20 dBm 60 GHz power amplifier with 32.4 dB Gain and 20 % Peak PAE in 65nm CMOS

E-band transformer-based differential 4-way power-combining amplifier

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