Optimized reversible binary-coded decimal adders

Thomsen, Michael Kirkedal; Glück, Robert

doi:10.1016/j.sysarc.2007.12.006

Cited by 42 publications

(22 citation statements)

References 13 publications

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“…4 and by plugging the synthesized combinational parts together, a reversible circuit results, composed of 1,139 circuit lines (including 867 lines with constant inputs), 5,047 Toffoli gates, and 1,692 Fredkin gates. Considering established cost metrics, this circuit has transistor costs of 504,904 (see [25] for more details on transistor costs) and quantum costs of 501,119 (see [26] for more details on quantum costs) 2 . Together with the external controller for the sequential components, this reversible circuit represents a CPU ready for running programs.…”

Section: Characteristics Of the Resulting Circuitmentioning

confidence: 99%

Designing a RISC CPU in Reversible Logic

Wille

Soeken

Große

et al. 2011

2011 41st IEEE International Symposium on Multiple-Valued Logic

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Abstract-Driven by its promising applications, reversible logic received significant attention. As a result, an impressive progress has been made in the development of synthesis approaches, implementation of sequential elements, and hardware description languages. In this paper, these recent achievements are employed in order to design a RISC CPU in reversible logic that can execute software programs written in an assembler language. The respective combinational and sequential components are designed using state-of-the-art design techniques.

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Section: Characteristics Of the Resulting Circuitmentioning

confidence: 99%

Designing a RISC CPU in Reversible Logic

Wille

Soeken

Große

et al. 2011

2011 41st IEEE International Symposium on Multiple-Valued Logic

View full text Add to dashboard Cite

show abstract

“…The table also depicts the runtime of the EA based tool to generate the output ordering. The quantum cost gives an estimate of the circuit cost in terms of the number of elementary gates [14], while the transistor cost gives an estimate of the circuit cost in terms of the number of CMOS transistors [18]. For circuits with inputs up to 9 from Table III we observe that reductions of up to 78.86% is observed with an average reduction of 18.52%.…”

Section: Experimental Setup and Resultsmentioning

confidence: 93%

An evolutionary approach to reversible logic synthesis using output permutation

Datta

Sengupta

Rahaman

et al. 2013

2013 8th IEEE Design and Test Symposium

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Abstract-The area of reversible circuit synthesis has become very important in recent years with the growing emphasis on low-power design and quantum computation. Many synthesis approaches have been reported over the last two decades. For small functions exact solutions can be computed. Otherwise, heuristics have to be applied that are either based on transformations or a direct mapping from a given data structure. Recently, it was shown that significant reduction in the cost of the synthesized circuits can be obtained, if the ordering of the output lines is changed. The drawback of the approach was that it can only be applied to smaller sized circuits.In this paper, an evolutionary approach for obtaining a good ordering of the output variables is proposed, which can be used for larger sized circuits as well. The method does not require explicit synthesis of the reversible circuit netlist. Experimental results are shown with respect to a transformation based synthesis tool. Reductions of up to 98% can be observed with an average reduction of 64.4% for larger circuits.

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“…• Transistor cost denotes the effort needed to realize a reversible circuit in CMOS according to [34] (with slight extensions). The transistor cost of a Toffoli or Fredkin gate is 8 · s where s is the number of control lines.…”

Section: Definitionmentioning

confidence: 99%

SyReC: a programming language for synthesis of reversible circuits

Wille¹,

Offermann²,

Drechsler³

2010

2010 Forum on Specification &Amp; Design Languages (FDL 2010)

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Abstract-Reversible logic serves as a basis for emerging technologies like quantum computing and additionally has applications in low-power design. In particular, since traditional technologies like CMOS are going to reach their limits in the near future, reversible logic has been established as a promising alternative. Thus, in the last years this area started to become intensely studied by researchers. In particular, how to efficiently synthesize complex reversible circuits is an important question. So far, only synthesis approaches are available that rely on Boolean function representations, like e.g. truth tables or decision diagrams.In this paper, we propose the programming language SyReC that allows to specify and afterwards to automatically synthesize reversible circuits. Using an existing programming language for reversible software design as basis, we introduce new concepts, operations, and restrictions allowing the specification of reversible hardware. Furthermore, a hierarchical approach is presented that automatically transforms the respective statements and operations of the new programming language into a reversible circuit. Experiments show that with the proposed method, complex circuits can be easily specified and synthesized while with previous approaches this often is not possible due to the limits caused by truth tables or decision diagrams.

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Optimized reversible binary-coded decimal adders

Cited by 42 publications

References 13 publications

Designing a RISC CPU in Reversible Logic

Designing a RISC CPU in Reversible Logic

An evolutionary approach to reversible logic synthesis using output permutation

SyReC: a programming language for synthesis of reversible circuits

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