Optimized Si-Cap Layer Thickness for Tensile-Strained-Si/ Compressively Strained SiGe Dual-Channel Transistors in 0.13 µm Complementary Metal Oxide Semiconductor Technology

Abstract

We report the fabrication of a tensile-strained-Si/compressively strained Si 0:72 Ge 0:28 dual-channel n-type metal-oxidesemiconductor field-effect transistor (NMOSFET) and p-type metal-oxide-semiconductor field-effect transistor (PMOSFET), which were grown on a relaxed Si 0:8 Ge 0:2 virtual substrate using the 0.13 mm CMOS process and we integrate both devices at the same wafer. It is found that a device based on such a structure that is good for optimizing NMOSFET and PMOSFET performance uses a thinner Si-cap layer of 5 nm for PMOSFET and a thicker Si-cap layer of approximately 15 nm for NMOSFET; this offers the most efficient enhancement of carrier mobility. By constraining the Si-cap layer thickness, the current drives of the N and PMOSFETs were increased by 16% and 12%, respectively, for channel lengths down to 0.13 um.

Investigation of Impact Ionization in Strained-Si n-Channel Metal–Oxide–Semiconductor Field-Effect Transistors

“…Detailed processes for strained-Si nMOSFETs with a relaxed Si 1Àx Ge x VS had been published elsewhere. 13) The unstrained-Si nMOSFETs studied as the control device were fabricated using the same complementary MOS (CMOS) process for comparison. The II measurement setup for strained-Si nMOSFETs with different strained-Si cap layer thicknesses of 10 and 15 nm at Ge contents x ¼ 15 and 20% is schematically illustrated in Fig.…”

Characteristics of Strained-Si nMOSFET Using Nickel Silicide Source/Drain

“…The large I on improvement for the strained-Si device is attributed to the reduction of the front-end process thermal budget and the avoidance of mobility degradation resulting from Ge out-diffusion and partial relaxation of the strained-Si layer. 8 As the Si-cap layer is thinner than 15 nm, the strained-Si channel mobility drops precipitously. The degradation of the channel mobility is attributed to the gradual consumption of the strained Si due to Ge out-diffusion diminishing the channel thickness that causes electron transmission in the SiGe layer and leads to an increase in carrier scattering and a loss of device performance.…”

“…In addition, the enhancement of strained-Si short-channel devices fell short of that expected from the longchannel characteristics. The performance degradation of shortchannel nMOSFETs is possibly attributed to the fact that conventional contact metallization with W/TiN/Ti 5 or metal silicide such as TiSi 2 6,7 and CoSi 2 8 was used in strained-Si narrow devices, and resulted in the difficulty to maintain a low contact resistance and a lower junction leakage. Simultaneously, process-induced variation effects become stronger for devices down to the deep submicrometer level.…”

Investigation of Transport Mechanism for Strained Si n Metal–Oxide–Semiconductor Field-Effect Transistor Grown on Multi-Layer Substrate

“…This is attributed to the Si-interstitials at Si/oxide interface were injected into the underneath Si-SiGe heterojunction, and the interstitials enhanced the Ge up-diffusion in the relaxed SiGe layer into the strained-Si/ oxide interface. 9) This Ge up-diffusion effect will make the Si-cap layer to be thinner. The thinner Si cap is insufficient to contain the inversion carrier, a substantial fraction of the electrons in the nMOSFET spill into the SiGe layer, which has lower electron mobility, and also in turn decreases the effective electron mobility in sample A.…”