We report the fabrication of a tensile-strained-Si/compressively strained Si 0:72 Ge 0:28 dual-channel n-type metal-oxidesemiconductor field-effect transistor (NMOSFET) and p-type metal-oxide-semiconductor field-effect transistor (PMOSFET), which were grown on a relaxed Si 0:8 Ge 0:2 virtual substrate using the 0.13 mm CMOS process and we integrate both devices at the same wafer. It is found that a device based on such a structure that is good for optimizing NMOSFET and PMOSFET performance uses a thinner Si-cap layer of 5 nm for PMOSFET and a thicker Si-cap layer of approximately 15 nm for NMOSFET; this offers the most efficient enhancement of carrier mobility. By constraining the Si-cap layer thickness, the current drives of the N and PMOSFETs were increased by 16% and 12%, respectively, for channel lengths down to 0.13 um.

In this paper, we report new process integration flows to fabricate strained-Si nMOSFETs having thicker strained-Si grown on a relaxed Si 0.8 Ge 0.2 virtual substrate. For the same device parameters and process condition, a device with this advanced integration flow (sample B) starting epitaxial strained-Si layers after shallow trench isolation and well implantation is shown having a 70% enhancement in effective electron mobility compared to the Si control device. Devices with conventional process sequences (sample A) exhibit a larger leakage current and up to 50% device failure. The leakage mechanism in sample A due to misfit dislocation-induced leakage paths is clearly demonstrated from the photon emission microscopy (PEM) measurement. Improved characteristics in sample B indicate that devices with new process sequences exhibit controlled misfit dislocations in strained-Si layers and show a greater flexibility for developing high-performance strained-Si CMOS.

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