Optimized system synthesis of complex RT level building blocks from multirate dataflow graphs

Horstmannshoff, Jens; Meyr, H.

doi:10.1109/isss.1999.814258

Cited by 12 publications

(16 citation statements)

References 4 publications

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“…The focus of these solutions is predominantly to deliver software implementations for processor targets. Hardware generation from dataflow models has also been extensively studied, e.g., in [19,33,12,15,13,28,5,23]. The goals of that line of work are akin to those of high-level synthesis, namely, obtaining efficient HW implementations automatically from high-level descriptions.…”

Section: Related Workmentioning

confidence: 99%

On tokens and signals: Bridging the semantic gap between dataflow models and hardware implementations

Tripakis

Limaye

Ravindran

et al. 2014

2014 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV)

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Dataflow models serve as useful abstractions of digital hardware in signal processing and other application domains. But when can one say that a certain dataflow model faithfully captures a given piece of hardware? The question is investigated in this paper. Finite state machines with synchronous semantics are used to model hardware. Asynchronous processes communicating via queues are employed for dataflow. A conformance relation between these two heterogeneous models of computation is developed that preserves performance properties such as worst-case throughput and latency.

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Section: Related Workmentioning

confidence: 99%

On tokens and signals: Bridging the semantic gap between dataflow models and hardware implementations

Tripakis

Limaye

Ravindran

et al. 2014

2014 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV)

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“…A large body of research exists on synthesizing hardware from dataflow models [1,5,10,13,14,15,19,35,37]. These works study problems similar to the glue design problem, however, some of them assume that hardware components for actors are to be synthesized, or at least that they have certain characteristics that match the proposed synthesis techniques.…”

Section: Related Workmentioning

confidence: 99%

“…For instance, Static Dataflow (SDF) 1 models have been applied to abstract hardware components [35,10,6]. Efficient algorithms are available for SDF models to compute performance metrics such as throughput and buffer sizes, as well as execution schedule [3,31,11,33,24,6].…”

Section: Introductionmentioning

confidence: 99%

Correct and non-defensive glue design using abstract models

Tripakis

Andrade

Ghosal

et al. 2011

Proceedings of the Seventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis

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Current hardware design practice often relies on integration of components, some of which may be IP or legacy blocks. While integration eases design by allowing modularization and component reuse, it is still done in a mostly ad hoc manner. Designers work with descriptions of components that are either informal or incomplete (e.g., documents in English, structural but non-behavioral specifications in IP-XACT) or too low-level (e.g., HDL code), and have little to no automatic support for stitching the components together. Providing such support is the glue design problem.This paper addresses this problem using a model-based approach. The key idea is to use high-level models, such as dataflow graphs, that enable efficient automated analysis. The analysis can be used to derive performance properties of the system (e.g., component compatibility, throughput, etc.), optimize resource usage (e.g., buffer sizes), and even synthesize low-level code (e.g., control logic). However, these models are only abstractions of the real system, and often omit critical information. As a result, the analysis outcomes may be defensive (e.g., buffers that are too big) or even incorrect (e.g., buffers that are too small). The paper examines these situations and proposes a correct and nondefensive design methodology that employs the right models to explore accurate performance and resource trade-offs.

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“…This parallel implementation results in the shortest processing delay but the largest hardware area, about 243,000 gates using 16 DCT1D resources in our experimentation. In Meyr's approach [5][8] [9], the synthesized hardware structure has one-to-one correspondence to the dataflow graph where a hardware resource is generated for each node. In Figure 4(b), one resource of DCT1D block is executed 8 times sequentially to consume and produce 64 samples while one invocation of DCT1D block is assumed to consume 8 samples at once 1 .…”

Section: Previous Work and Motivational Examplementioning

confidence: 99%

“…It means that we need input (or output) buffers to store as many input (or output) samples as specified at each input(output) port. In Meyr's work [9], a node consumes or produces one sample at each invocation. Consider a simple example of Figure 9.…”

Section: Block Typesmentioning

confidence: 99%

Hardware synthesis from coarse-grained dataflow specification for fast HW/SW cosynthesis

Jung

2004

Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis - CODES+ISSS

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This paper concerns automatic hardware synthesis from data flow graph (DFG) specification for fast HW/SW cosynthesis. A node in DFG represents a coarse grain block such as FIR and DCT and a port in a block may consume multiple data samples per invocation, which distinguishes our approach from behavioral synthesis and complicates the problem. In the presented design methodology, a dataflow graph with specified algorithm can be mapped to various hardware structures according to the resource allocation and schedule information. This simplifies the management of the area/performance tradeoff in hardware design and widens the design space of hardware implementation of a dataflow graph compared with the previous approaches. Through experiments with some examples, the usefulness of the proposed technique is demonstrated.

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Optimized system synthesis of complex RT level building blocks from multirate dataflow graphs

Cited by 12 publications

References 4 publications

On tokens and signals: Bridging the semantic gap between dataflow models and hardware implementations

On tokens and signals: Bridging the semantic gap between dataflow models and hardware implementations

Correct and non-defensive glue design using abstract models

Hardware synthesis from coarse-grained dataflow specification for fast HW/SW cosynthesis

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