Optimized task graph mapping on a many-core neuromorphic supercomputer

Sugiarto, Indar; Campos, Pedro; Dahir, Nizar; Tempesti, Gianluca; Furber, Steve

doi:10.1109/hpec.2017.8091066

Cited by 7 publications

(9 citation statements)

References 9 publications

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“…In [92], Sugiarto et al propose a framework to map general purpose applications running as a task graph on to the SpiNNaker hardware, with the objective of reducing the data traffic between different SpiNNaker chips. The proposed framework uses the task graph description given by XL-Stage program [93].…”

Section: System Software For Performance and Energy Optimizationmentioning

confidence: 99%

“…Summary: Table 3 summarizes these approaches. SentryOS [85] µBrain [20] Throughput, Utilization Compiler and run-time manager Corelet [87] TrueNorth [26] Core Utilization Compiler framework LCompiler [88] Loihi [25] Core Utilization Compiler framework PACMAN [89], [92] SpiNNaker [23] Core Utilization Compiler framework SNN-PP [104], [106,107] SpiNNaker [23] Spike Communication Energy Compiler and run-time manager PyNN [90] SpiNNaker [23], BrainScaleS [22], Loihi [25] Core Utilization Compiler framework…”

Section: System Software For Performance and Energy Optimizationmentioning

confidence: 99%

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Implementing Spiking Neural Networks on Neuromorphic Architectures: A Review

Huynh¹,

Varshika²,

Paul³

et al. 2022

Preprint

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Recently, both industry and academia have proposed several different neuromorphic systems to execute machine learning applications that are designed using Spiking Neural Networks (SNNs). With the growing complexity on design and technology fronts, programming such systems to admit and execute a machine learning application is becoming increasingly challenging. Additionally, neuromorphic systems are required to guarantee real-time performance, consume lower energy, and provide tolerance to logic and memory failures. Consequently, there is a clear need for system software frameworks that can implement machine learning applications on current and emerging neuromorphic systems, and simultaneously address performance, energy, and reliability. Here, we provide a comprehensive overview of such frameworks proposed for both, platform-based design and hardware-software co-design. We highlight challenges and opportunities that the future holds in the area of system software technology for neuromorphic computing.

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Section: System Software For Performance and Energy Optimizationmentioning

confidence: 99%

Section: System Software For Performance and Energy Optimizationmentioning

confidence: 99%

Implementing Spiking Neural Networks on Neuromorphic Architectures: A Review

Huynh¹,

Varshika²,

Paul³

et al. 2022

Preprint

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“…Our method for implementing fpGA based on the idea of run-time improvement; here, the multi-core feature of SpiNNaker chips provides a redundancy that can be exploit for amelioration. Here, we propose to use the similar approach presented in our previous work (see [36]), where we use a spawning task mechanism on several cores for improving performance through local parallelism (i.e., those cores will be loaded with the Ì ISSN: 1693-6930 same GA code and work in synchrony) and the rest of the cores will serve as the backup cores for providing higher reliability through a fault tolerance mechanism.…”

Section: Realisation In Spinnakermentioning

confidence: 99%

Fine-grained or coarse-grained? Strategies for implementing parallel genetic algorithms in a programmable neuromorphic platform

Sugiarto¹,

Furber²

2021

TELKOMNIKA

Self Cite

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Genetic algorithm (GA) is one of popular heuristic-based optimization methods that attracts engineers and scientists for many years. With the advancement of multiand many-core technologies, GAs are transformed into more powerful tools by parallelising their core processes. This paper describes a feasibility study of implementing parallel GAs (pGAs) on a SpiNNaker. As a many-core neuromorphic platform, SpiNNaker offers a possibility to scale-up a parallelised algorithm, such as a pGA, whilst offering low power consumption on its processing and communication overhead. However, due to its small packets distribution mechanism and constrained processing resources, parallelising processes of a GA in SpiNNaker is challenging. In this paper we show how a pGA can be implemented on SpiNNaker and analyse its performance. Due to inherently numerous parameter and classification of pGAs, we evaluate only the most common aspects of a pGA and use some artificial benchmarking test functions. The experiments produced some promising results that may lead to further developments of massively parallel GAs on SpiNNaker. This is an open access article under the CC BY-SA license.

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“…Some groups are thus working on algorithms to perform optimized mapping of any trained network onto neuromorphic hardware [37,50]. Others exploit graph theory to maximise parallelization at the computation diagram level [2,173].…”

Section: Algorithm To Hardwarementioning

confidence: 99%

Spiking Neural Networks Hardware Implementations and Challenges

Bouvier

Valentian

Mesquida

et al. 2019

J. Emerg. Technol. Comput. Syst.

194

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Neuromorphic computing is henceforth a major research field for both academic and industrial actors. As opposed to Von Neumann machines, brain-inspired processors aim at bringing closer the memory and the computational elements to efficiently evaluate machine-learning algorithms. Recently, Spiking Neural Networks, a generation of cognitive algorithms employing computational primitives mimicking neuron and synapse operational principles, have become an important part of deep learning. They are expected to improve the computational performance and efficiency of neural networks, but are best suited for hardware able to support their temporal dynamics. In this survey, we present the state of the art of hardware implementations of spiking neural networks and the current trends in algorithm elaboration from model selection to training mechanisms. The scope of existing solutions is extensive; we thus present the general framework and study on a case-by-case basis the relevant particularities. We describe the strategies employed to leverage the characteristics of these event-driven algorithms at the hardware level and discuss their related advantages and challenges.

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Optimized task graph mapping on a many-core neuromorphic supercomputer

Cited by 7 publications

References 9 publications

Implementing Spiking Neural Networks on Neuromorphic Architectures: A Review

Implementing Spiking Neural Networks on Neuromorphic Architectures: A Review

Fine-grained or coarse-grained? Strategies for implementing parallel genetic algorithms in a programmable neuromorphic platform

Spiking Neural Networks Hardware Implementations and Challenges

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