Optimized Threshold Voltage Variation for Tunable Body Biasing CMOS Power Amplifier

Kumar, Sandeep; Handa, Mitul; Bhasin, Himanshu; Kanaujia, Binod Kumar; Dwari, Santanu; Gautam, A. K.

doi:10.1007/s11277-016-3469-4

Cited by 2 publications

(1 citation statement)

References 11 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…So, it cannot be accepted as a beneficial solution. Recently, many papers have been reported in the literature to reduce the circuit overdesign while increasing its robustness against reliability effects [56][57][58][59][60][61]. For instance, in [59], Yuan et al proposed an adaptive gate-source biasing circuit to keep the overdrive voltage of a metal-oxide-semiconductor field-effect transistor (MOSFET) constant, and its performance was then verified for the reliability design of a class AB power amplifier.…”

Section: Introductionmentioning

confidence: 99%

Design and Analysis of a Low-Voltage VCO: Reliability and Variability Performance

Azadmousavi,

Ghafar-Zadeh

2023

Micromachines

View full text Add to dashboard Cite

This paper investigates an adaptive body biasing (ABB) circuit to improve the reliability and variability of a low-voltage inductor–capacitor (LC) voltage-controlled oscillator (VCO). The ABB circuit provides VCO resilience to process variability and reliability variation through the threshold voltage adjustment of VCO’s transistors. Analytical equations considering the body bias effect are derived for the most important relations of the VCO and then the performance is verified using the post-layout simulation results. Under a 0.16% threshold voltage shift, the sensitivity of the normalized phase noise and transconductance of the VCO with the ABB circuit compared to the constant body bias (CBB) decreases by around 8.4 times and 3.1 times, respectively. Also, the sensitivity of the normalized phase noise and transconductance of the proposed VCO under 0.16% mobility variations decreases by around 1.5 times and 1.7 times compared to the CBB, respectively. The robustness of the VCO is also examined using process variation analysis through Monte Carlo and corner case simulations. The post-layout results in the 180 nm CMOS process indicate that the proposed VCO draws a power consumption of only 398 µW from a 0.6 V supply when the VCO frequency is 2.4 GHz. It achieves a phase noise of −123.19 dBc/Hz at a 1 MHz offset and provides a figure of merit (FoM) of −194.82 dBc/Hz.

show abstract