Optimizing Compiler for the CELL Processor

Eichenberger, Alexandre E.; O’Brien, Kevin; Wu, Peng; Chen, Tong; Oden, P. H.; Prener, Daniel A.; Shepherd, J. C.; So, Byoungro; Sura, Zehra; Wang, A.; Zhang, Tao; Zhao, Peng; Gschwind, Michael

doi:10.1109/pact.2005.33

Cited by 122 publications

(81 citation statements)

References 29 publications

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“…The purpose is to evolve OpenMP into an appropriate programming model for many-core processors with explicitly managed memory hierarchy [21], e.g. the IBM CELL [22] and the IBM Cyclops-64 [23] processor.…”

Section: Future Workmentioning

confidence: 99%

Tile Reduction: The First Step towards Tile Aware Parallelization in OpenMP

Gao

Wang

Manzano

et al. 2009

Evolving OpenMP in an Age of Extreme Parallelism

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Abstract. Tiling is widely used by compilers and programmer to optimize scientific and engineering code for better performance. Many parallel programming languages support tile/tiling directly through first-class language constructs or library routines. However, the current OpenMP programming language is tile oblivious, although it is the de facto standard for writing parallel programs on shared memory systems. In this paper, we introduce tile aware parallelization into OpenMP. We propose tile reduction, an OpenMP tile aware parallelization technique that allows reduction to be performed on multi-dimensional arrays. The paper has three contributions: (a) it is the first paper that proposes and discusses tile aware parallelization in OpenMP. We argue that, it is not only necessary but also possible to have tile aware parallelization in OpenMP; (b) the paper introduces the methods used to implement tile reduction, including the required OpenMP API extension and the associated code generation techniques; (c) we have applied tile reduction on a set of benchmarks. The experimental results show that tile reduction can make parallelization more natural and flexible. It not only can expose more parallelism in a program, but also can improve its data locality.

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Section: Future Workmentioning

confidence: 99%

Tile Reduction: The First Step towards Tile Aware Parallelization in OpenMP

Gao

Wang

Manzano

et al. 2009

Evolving OpenMP in an Age of Extreme Parallelism

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“…In the remainder of this section we examine the approaches for mapping BDV algorithm across the CELL clusters and within the CELL. Compiler assisted parallelization using IBM XL compiler [31] will be part of our future studies.…”

Section: Mapping Bdv Onto the Ibm Cellmentioning

confidence: 99%

“…This small memory size influences the way code and data for the applications are partitioned across the CELL. For many programs with a small code size, function overlaying and resident partition management [31] might not be necessary. The total code size for the B-U computation is about 25 KB and hence no function overlaying mechanism was used in our implementation.…”

Section: Application Data Analysismentioning

confidence: 99%

“…The labels indicated in the last column corresponds to different stages in Fig. 7 To reduce this constraint, various techniques such as software cache, double buffering, pre-fetching [31], etc., can be used depending upon the data access pattern. Some important data structures used by the program and its properties are listed in Table 1.…”

Section: Application Data Analysismentioning

confidence: 99%

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Brain Derived Vision Algorithm on High Performance Architectures

Nageswaran

Felch

Chandrasekhar

et al. 2009

Int J Parallel Prog

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Even though computing systems have increased the number of transistors, the switching speed, and the number of processors, most programs exhibit limited speedup due to the serial dependencies of existing algorithms. Analysis of intrinsically parallel systems such as brain circuitry have led to the identification of novel architecture designs, and also new algorithms than can exploit the features of modern multiprocessor systems. In this article we describe the details of a brain derived vision (BDV) algorithm that is derived from the anatomical structure, and physiological operating principles of thalamo-cortical brain circuits. We show that many characteristics of the BDV algorithm lend themselves to implementation on IBM CELL architecture, and yield impressive speedups that equal or exceed the performance of specialized solutions such as FPGAs. Mapping this algorithm to the IBM CELL is non-trivial, and we suggest various approaches to deal with parallelism, task granularity, communication, and memory locality. We also show that a cluster of three PS3s (or more) containing IBM CELL processors provides a promising platform for brain derived algorithms, exhibiting speedup of more than 140× over a desktop PC implementation, and thus enabling real-time object recognition for robotic systems.

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“…The first is a software-caching technique, which emulates the behavior of a hardware cache by the software. The most representative example of such methods is the local memory in the CELL BE processor [2]. However, there is no highly successful scheme to eliminate the high address translation overhead at runtime, because a single memory reference instruction is replaced by a couple of instructions for softwareemulated cache lookups.…”

Section: Introductionmentioning

confidence: 99%

Core Working Set Based Scratchpad Memory Management

Deng

et al. 2011

IEICE Trans. Inf. & Syst.

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SUMMARYMany state-of-the-art embedded systems adopt scratchpad memory (SPM) as the main on-chip memory due to its advantages in terms of energy consumption and on-chip area. The cache is automatically managed by the hardware, while SPM is generally manipulated by the software. Traditional compiler-based SPM allocation methods commonly use static analysis and profiling knowledge to identify the frequently used data during runtime. The data transfer is determined at the compiling stage. However, these methods are fragile when the access pattern is unpredictable at compile time. Also, as embedded devices diversify, we expect a novel SPM management that can support embedded application portability over platforms. This paper proposes a novel runtime SPM management method based on the core working set (CWS) theory. A counting-based CWS identification algorithm is adopted to heuristically determine those data blocks in the program's working set with high reference frequency, and then these promising blocks are allocated to SPM. The novelty of this SPM management method lies in its dependence on the program's dynamic access pattern as the main cue to conduct SPM allocation at runtime, thus offloading SPM management from the compiler. Furthermore, the proposed method needs the assistance of MMU to complete address redirection after data transfers. We evaluate the new approach by comparing it with the cache system and a classical profiling-driven method, and the results indicate that the CWS-based SPM management method can achieve a considerable energy reduction compared with the two reference systems without notable degradation on performance. key words: embedded processor, scratchpad memory management, core working set

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Optimizing Compiler for the CELL Processor

Cited by 122 publications

References 29 publications

Tile Reduction: The First Step towards Tile Aware Parallelization in OpenMP

Tile Reduction: The First Step towards Tile Aware Parallelization in OpenMP

Brain Derived Vision Algorithm on High Performance Architectures

Core Working Set Based Scratchpad Memory Management

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