Optimizing FinFET parameters for minimizing short channel effects

Kumar, Abhishek; Singh, Sruti Suvadarsini

doi:10.1109/iccsp.2016.7754396

Cited by 10 publications

(3 citation statements)

References 5 publications

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“…As a result, V T,lin , SS, and DIBL were extracted with similar values regardless of W NS for both experiments and simulation. Increasing the channel width in FinFETs and GAA MOS-FETs with thick gate insulators or channels is well known to be vulnerable to SCEs [21][22][23]. However, since the T NS of the fabricated GAA SiNS MOSFETs is extremely thin (6 nm), the channel potential is effectively controlled by the V GS regardless of W NS .…”

Section: Measurement Results and Discussionmentioning

confidence: 99%

Design study of the gate-all-around silicon nanosheet MOSFETs

Lee

Park

Choi

et al. 2020

Semicond. Sci. Technol.

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The gate-all-around (GAA) silicon nanosheet (SiNS) metal-oxide-semiconductor field-effect transistor (MOSFET) structures have been recognized as excellent candidates to achieve improved power performance and area scaling compared to the current FinFET technologies. Specifically, SiNS structures provide high drive currents due to wide effective channel width (W eff ) while maintaining short-channel control. In this paper, we fabricate a GAA SiNS MOSFET fully surrounded by a gate with a gate length (L G ) of 22 nm, a SiNS width (W NS ) of 23 nm, and SiNS thickness (T NS ) of 6 nm. In addition, the fabricated GAA SiNS MOSFETs were evaluated for electrostatic characteristics and short-channel effects (SCEs) according to various channel length and width dimensions. We confirmed that the GAA SiNS MOSFET showed similar short-channel controllability regardless of W NS due to the extremely thin T NS . In addition, we analyzed SCEs of GAA SiNS MOSFETs with different T NS through simulation.

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Section: Measurement Results and Discussionmentioning

confidence: 99%

Design study of the gate-all-around silicon nanosheet MOSFETs

Lee

Park

Choi

et al. 2020

Semicond. Sci. Technol.

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“…It is worth indicating that by scaling, we mean that the effective channel length is reduced by a scale of S. However, scaling can be challenging because when we reduce channel length by a scale S (for ¡ 100 nm technology) some parameters have to be changed to preserve currents and voltage relations in MOSFET, as described later. In addition, some nonlinearities will appear and should be taken into consideration [26].…”

Section: Scalingmentioning

confidence: 99%

An efficient design of 45-nm CMOS low-noise charge sensitive amplifier for wireless receivers

Almalkawi

Al-Bqerat²,

Itradat

et al. 2022

IJECE

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<p>Amplifiers are widely used in signal receiving circuits, such as antennas, medical imaging, wireless devices and many other applications. However, one of the most challenging problems when building an amplifier circuit is the noise, since it affects the quality of the intended received signal in most wireless applications. Therefore, a preamplifier is usually placed close to the main sensor to reduce the effects of interferences and to amplify the received signal without degrading the signal-to-noise ratio. Although different designs have been optimized and tested in the literature, all of them are using larger than 100 nm technologies which have led to a modest performance in terms of equivalent noise charge (ENC), gain, power consumption, and response time. In contrast, we consider in this paper a new amplifier design technology trend and move towards sub 100 nm to enhance its performance. In this work, we use a pre-well-known design of a preamplifier circuit and rebuild it using 45 nm CMOS technology, which is made for the first time in such circuits. Performance evaluation shows that our proposed scaling technology, compared with other scaling technology, extremely reduces ENC of the circuit by more than 95%. The noise spectral density and time resolution are also reduced by 25% and 95% respectively. In addition, power consumption is decreased due to the reduced channel length by 90%. As a result, all of those enhancements make our proposed circuit more suitable for medical and wireless devices.</p>

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“…However, reducing device dimensions generate short channel effects, (SCEs) [8][9][10][11][12][13][14] in single gate MOSFETs, which negatively influence current and cause off-state leakage. To address these challenges, FinFETs stand out as prospective electronic devices [15][16][17][18][19][20][21][22][23][24][25][26][27][28][29][30] due to their improved scalability and ability to control SCEs. The functionality of nanoscale FinFETs is now transitioning into a region where quantum mechanical effects such as quantum confinement effects are becoming discernible [31][32].…”

Section: Introductionmentioning

confidence: 99%

Effect of electron mobility variation on short channel effects in nanoscale double gate FinFETs: A comparative study

Shehu,

Garba Babaji,

Mutari Hajara Ali

2024

IJPR

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This work investigates the impact of electron mobility variations on short channel effects (SCEs) in different semiconductor materials using FinFETs. Using PADRE simulator, the work examines Gallium Arsenide (GaAs), Gallium Antimonide (GaSb), Gallium Nitride (GaN), and Silicon (Si) FinFETs, analyzing performance metrics such as Drain Induced Barrier Lowering (DIBL), Subthreshold Swing (SS) and Threshold Voltage roll-off. The result shows that GaN-FinFET exhibits lowest subthreshold swing of 63 mV/dec at electron mobility of 10000 cm2/Vs, and threshold voltage of 0.44V at electron mobility of 10000 cm2/Vs, while Si-FinFET exhibits lowest DIBL of 3 mV/V at (4000-10000) cm2/Vs. This finding contributes to advancing the understanding of short channel effects in nanoscale FinFETs and provides valuable insights for optimizing device performance in future semiconductor technologies.

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Optimizing FinFET parameters for minimizing short channel effects

Cited by 10 publications

References 5 publications

Design study of the gate-all-around silicon nanosheet MOSFETs

Design study of the gate-all-around silicon nanosheet MOSFETs

An efficient design of 45-nm CMOS low-noise charge sensitive amplifier for wireless receivers

Effect of electron mobility variation on short channel effects in nanoscale double gate FinFETs: A comparative study

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