Optimizing MLC-based STT-RAM caches by dynamic block size reconfiguration

Abstract

The use of STT-RAM as on-chip caches has been widely studied. However, existing works focused mainly on singlelevel cell (SLC) design while the potential of multi-level cell (MLC) STT-RAM has not yet been fully explored. It is expected that MLC STT-RAM can achieve 2× the storage density of SLC and thus improves system performance. Unfortunately, at the device level, the two-step read/write scheme introduces performance and energy overhead. In this paper, we propose an architectural design to dynamically reconfigure the cache block size for a MLC STT-RAM last-level cache. Our approach place certain hot data chunks in smaller blocks so as to benefit from the lower latency and energy, while keeping the rest in larger blocks to maintain an overall hit rate. Experiment shows that our strategy reduces the performance and energy penalty of MLC STT-RAM caches with a slightly higher miss rate. On average, IPC is increased by 4.6% while energy consumption is reduced by 23.5% compared to the conventional MLC STT-RAM cache.

Extending multi‐level STT‐MRAM cell lifetime by minimising two‐step and hard state transitions in hot bits

“…MLC write operations as demonstrated earlier are slower and energy-consuming compared with the SLC case. During the past few decades, several encoding methods have been proposed to reduce write energy and increase STT-MRAM lifetime [20][21][22][23][24][25][26][27][28][29][30][31][32][33]. Since, both read energy and latency of STT-MRAM are very low, replacing a write operation with a read-modify-write operation is an efficient way to reduce energy consumption.…”

“…To avoid two‐step write transitions, Wang et al [29] proposed a technique to dynamically reconfigure block size in such a way that only soft domains are used for hot data, while less frequently used data blocks use both domains. MFNW [30] extends Flip‐N‐Write [31] encoding solution to MLC NVMs to reduce average energy consumption and improve endurance.…”

“…To address latency and power issues, data encoding solutions [20–33] have been proposed for STT‐MRAM. These approaches enhance energy characteristics of such memories by re‐encoding application data to increase energy‐efficient states and reduce inefficient ones.…”

TLC STT-MRAM aware LLC for multicore processor

“…Such complex resistance state transition and detection processes for write and read operations, respectively, seriously degrade performance, power consumption, and endurance. Previous works have mitigated the degradation of multi-level cell (MLC) STT-MRAMs [12,17,18,19,20,21,22,23,24,25,26,27], but they are not effective for a large LLC comprised of series TLC STT-MRAMs. In this paper, we propose the architecture and operation of a novel LLC comprised of series TLC STT-MRAMs.…”