Optimizing product yield using manufacturing defect weights

Bickford, Jeanne Paulette; Hibbeler, Jason; Peyer, Sven; Mueller, Dirk; Kumar, Vasanth S.

doi:10.1109/asmc.2012.6212861

Cited by 4 publications

(1 citation statement)

References 21 publications

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“…Weight, as used in this context, can be considered to be a product of the criticality of a component or geometric feature and the risk in a given geometric context. Indeed, computations of this type are applied in various risk assessment schemes such as Failure Mode and Effect Analysis (FMEA) [15], [16]. As such, both the criticality and risk values are empirically determined and assigned by the foundry.…”

Section: B Interconnect Costmentioning

confidence: 99%

MIDAS: Model for IP-inclusive DFM assessment of system manufacturability

Subramaniyan

Larsson-Edefors

2014

2014 5th European Workshop on CMOS Variability (VARI)

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Complex system implementations combined with the latest technology nodes allow us to implement hardware for versatile applications. The ever increasing demand for quick time-to-market has led to the widespread use of Intellectual Property (IP) in ASIC design methodologies. These developments, in addition to manufacturing limitations, make early prediction of manufacturability for complete systems challenging. We present MIDAS: a scalable, IP-inclusive model to predict system manufacturability. Results from applying MIDAS to an embedded processor system reveals that several useful insights can be gained towards realizing yield budgets for complex systems allowing quicker co-optimization of all implementation goals.

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Section: B Interconnect Costmentioning

confidence: 99%