Optimizing the front and back biases for the best sense margin and retention time in UTBOX FBRAM

Almeida, Luciana O.; Sasaki, K. R. A.; Caillat, C.; Aoulaiche, M.; Collaert, N.; Jurczak, M.; Simoen, Eddy; Claeys, Cor; Martino, João Antônio

doi:10.1016/j.sse.2013.02.038

Cited by 26 publications

(13 citation statements)

References 13 publications

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“…In order to illustrate the competitiveness of both RFET topologies for embedded 1T-DRAM, their energy consumption during write and read operations is compared with the existing capacitorless DRAM, [39][40][41][42][43][44][45][46][47][48][49][50] and the same is shown in Table III. These results, extracted from published data, depending on the read/write time considered in the analysis.…”

Section: Assessment Of 1t-dram Metricsmentioning

confidence: 99%

“…However, even in such a scenario, we expect constraints of energy consumption on sense margin, retention and read/ write speed. Nevertheless, results in Table III indicate that RFET2 architectures consume significantly lower write energy compared to Ultra-thin BOX FET Floating body RAM, 39) SiGe quantum well FET, 40) 2 T Thyristor RAM, 41) Double gate GaAs JL FET, 42) Twin gate TFET, 43) L-Shaped TFET, 44) Ge/GaAs heterojunction TFET, 45) Z2 FET, 46) and RFET1. However, shell-doped JLFET, 47) raised source/drain MOSFET, 48) Twin gate TFET, 43) Si 0.6 Ge 0.4 Bipolar IMOS, 49) and Ge/GaAs heterojunction TFET 45) show overall lesser energy consumption compared to RFET2.…”

Section: Assessment Of 1t-dram Metricsmentioning

confidence: 99%

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Architectural evaluation of programmable transistor-based capacitorless DRAM for high-speed system-on-chip applications

Nirala

Roy

Semwal

et al. 2023

Jpn. J. Appl. Phys.

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High-speed write/read operation and low energy consumption along with a lower footprint are prerequisites for one transistor (1T) embedded DRAM (eDRAM). This work evaluates the suitability of two different reconfigurable transistors (RFET) architectures for implementing 1T-eDRAM based on key metrics such as high-temperature operation, speed, scalability, and energy consumption. Amongst the two topologies, a twin gate RFET (with one control and program gate each on top and bottom gate oxide) is better suited for 1T-eDRAM due to (i) fast write (1 ns) and read (1 ns) operations, (ii) scalability down to a total source-to-drain length of 60 nm, (iii) better sense margin, and (iv) lower energy consumption during write operation. However, RFET topology with two program gates and one control gates (each on top and bottom gate oxide) shows an enhanced retention time but at the expense of higher energy consumption which may be detrimental for energy efficient system-on-chip applications.

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Section: Assessment Of 1t-dram Metricsmentioning

confidence: 99%

Section: Assessment Of 1t-dram Metricsmentioning

confidence: 99%

Architectural evaluation of programmable transistor-based capacitorless DRAM for high-speed system-on-chip applications

Nirala

Roy

Semwal

et al. 2023

Jpn. J. Appl. Phys.

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“…Research shows that reading “0” current of DGTFET DRAM can reach to 1 nA/μm, which is much less than that of traditional 1T1C DRAM. And the RT of 2 s is far superior to the target value of 64 ms which is usually set to dynamic refresh time in computing system [ 21 ]. The RT of DGTFET DRAM is still larger than 300 ms when the temperature is increased to 85 °C, which authorizes its practicability in the harsh conditions.…”

Section: Introductionmentioning

confidence: 99%

The Optimization of Spacer Engineering for Capacitor-Less DRAM Based on the Dual-Gate Tunneling Transistor

Liu

Wang

et al. 2018

Nanoscale Res Lett

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The DRAM based on the dual-gate tunneling FET (DGTFET) has the advantages of capacitor-less structure and high retention time. In this paper, the optimization of spacer engineering for DGTFET DRAM is systematically investigated by Silvaco-Atlas tool to further improve its performance, including the reduction of reading “0” current and extension of retention time. The simulation results show that spacers at the source and drain sides should apply the low-k and high-k dielectrics, respectively, which can enhance the reading “1” current and reduce reading “0” current. Applying this optimized spacer engineering, the DGTFET DRAM obtains the optimum performance-extremely low reading “0” current (10−14A/μm) and large retention time (10s), which decreases its static power consumption and dynamic refresh rate. And the low reading “0” current also enhances its current ratio (107) of reading “1” to reading “0”. Furthermore, the analysis about scalability reveals its inherent shortcoming, which offers the further investigation direction for DGTFET DRAM.

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“…The single transistor capacitorless dynamic random access memory (DRAM) has overcome scalability issue associated with traditional capacitors in the conventional 1T-1C configuration [1][2][3][4][5][6][7][8][9][10][11]. The voltage scalability concerns of conventional metal-oxide-semiconductor (MOS) transistors can be circumvented using steep switching tunnel field effect transistors (TFETs) [12][13][14][15][16][17] which exhibit a sub-60 mV/ decade off-to-on transition.…”

Section: Introductionmentioning

confidence: 99%

Overcoming the drawback of lower sense margin in tunnel FET based dynamic memory along with enhanced charge retention and scalability

Navlakha

Kranti²

2017

Nanotechnology

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The work reports on the use of a planar tri-gate tunnel field effect transistor (TFET) to operate as dynamic memory at 85 °C with an enhanced sense margin (SM). Two symmetric gates (G1) aligned to the source at a partial region of intrinsic film result into better electrostatic control that regulates the read mechanism based on band-to-band tunneling, while the other gate (G2), positioned adjacent to the first front gate is responsible for charge storage and sustenance. The proposed architecture results in an enhanced SM of ∼1.2 μA μm along with a longer retention time (RT) of ∼1.8 s at 85 °C, for a total length of 600 nm. The double gate architecture towards the source increases the tunneling current and also reduces short channel effects, enhancing SM and scalability, thereby overcoming the critical bottleneck faced by TFET based dynamic memories. The work also discusses the impact of overlap/underlap and interface charges on the performance of TFET based dynamic memory. Insights into device operation demonstrate that the choice of appropriate architecture and biases not only limit the trade-off between SM and RT, but also result in improved scalability with drain voltage and total length being scaled down to 0.8 V and 115 nm, respectively.

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Optimizing the front and back biases for the best sense margin and retention time in UTBOX FBRAM

Cited by 26 publications

References 13 publications

Architectural evaluation of programmable transistor-based capacitorless DRAM for high-speed system-on-chip applications

Architectural evaluation of programmable transistor-based capacitorless DRAM for high-speed system-on-chip applications

The Optimization of Spacer Engineering for Capacitor-Less DRAM Based on the Dual-Gate Tunneling Transistor

Overcoming the drawback of lower sense margin in tunnel FET based dynamic memory along with enhanced charge retention and scalability

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