Optimizing transistor networks using a graph-based technique

Transistor-level optimization of CMOS complex gates

“…Therefore, the switch network is generated during the step (B), applying edges sharing technique presented in [12].…”

“…For each of these five cases, such topological composition is done gradually until achieving a network that is logically equivalent to the input Boolean function. During the composition process, the edges sharing procedure is applied to the network in order to eliminate redundant switches [12]. Such strategy allows a reduction in the total number of switches.…”

“…This graph can be optimized by edges sharing [10][11][12] or can be gradually composed from an input expression [13]. In some cases, these techniques are able to deliver better results than factorization based methods if nonseries-parallel (NSP) arrangements are able to be found during the graph manipulation process.…”

“…In some cases, these techniques are able to deliver better results than factorization based methods if nonseries-parallel (NSP) arrangements are able to be found during the graph manipulation process. Such optimization obtained exploiting NSP topologies is due to the large sharing between the paths that represent cubes of a function, so reducing the total switch count and overcoming SP arrangements [10,12,13]. This paper proposes a new graph-based method able to generate optimized transistor networks.…”

“…Our approach presents a structural algorithm based on SP arrangements to avoid unnecessary computation during the generation of transistor networks. Different from the approach presented in [12], this new method delivers the networks not only applying transistor sharing, but also considering topological information during the generation process. Moreover, this paper presents a methodology based on SP kernels different from previous method described in [14], in which the NSP Kernel concept was introduced.…”