Optimum ArFi laser bandwidth for 10nm node logic imaging performance

Abstract

1Cost and cycle time of multiple patterning -especially for more than 2x 2 Process control on key parameters such as overlay, CD control, LWR with multiple patterning 3 EUV Source power 4 EUV Mask Infrastructure (defect inspection and verification, mitigation, mask lifetime) Defect free EUV mask blanks, mask availability 5 EUV resist and/or process that meets sensitivity, resolution, LER requirements 1 6 DSA defecti ity and positional accuracy ABSTRACT Lithography process window (PW) and CD uniformity (CDU) requirements are being challenged with scaling across all device types. Aggressive PW and yield specifications put tight requirements on scanner performance, especially on focus budgets resulting in complicated systems for focus control. In this study, an imec N10 Logic-type test vehicle was used to investigate the E95 bandwidth impact on six different Metal 1 Logic features. The imaging metrics that track the impact of light source E95 bandwidth on performance of hot spots are: process window (PW), line width roughness (LWR), and local critical dimension uniformity (LCDU).In the first section of this study, the impact of increasing E95 bandwidth was investigated to observe the lithographic process control response of the specified logic features. In the second section, a preliminary assessment of the impact of lower E95 bandwidth was performed. The impact of lower E95 bandwidth on local intensity variability was monitored through the CDU of line end features and the LWR power spectral density (PSD) of line/space patterns. The investigation found that the imec N10 test vehicle (with OPC optimized for standard E95 bandwidth of300fm) features exposed at 200fm showed pattern specific responses, suggesting areas of potential interest for further investigation.

Pattern deformation mitigation for EUV photoresists using wafer backside cleaning techniques

“…In typical semiconductor manufacturing, CVD is mostly performed before the lithographic patterning process. 28,29) For this reason, the CVD process is considered as a main source of backside particle contamination (e.g. metallic particles).…”

Mitigation of EUV photoresist pattern deformation by wafer backside cleaning techniques

“…In typical semiconductor manufacturing, chemical vapor deposition (CVD) is mostly performed before the lithographic patterning process 28,29) . For this reason, the CVD process is considered as a main source of backside particle contamination (e.g.…”

Photolithography in the vacuum ultraviolet (172 nm) with sub-400 nm resolution: photoablative patterning of nanostructures and optical components in bulk polymers and thin films on semiconductors

“…However, it was the transition to the shorter wavelengths afforded by the ArF (193 nm) and KrF (248 nm) excimer lasers, introduced to photolithography by Jain et al 4 in 1982, that accelerated the drive to realizing sub-100 nm features and, specifically, has resulted in the remarkable achievement of reaching the 14 nm node with 193 nm exposure systems. 5,6 Although pulsed, deepultraviolet lasers (having wavelengths of ∼200-250 nm) and, more recently, laser-produced tin plasma sources at 13.5 nm (in the extreme ultraviolet (EUV) spectral region) can be credited with the relentless shrinkage in feature sizes, this progress has come at a substantial cost. Increasingly sophisticated steppers and the expense associated with their acquisition and maintenance have progressively limited access to state-of-the art photolithographic tools.…”