Optoelectronic systems based on InGaAs–complementary-metal-oxide-semiconductor smart-pixel arrays and free-space optical interconnects

Abstract

Free-space optical interconnects have been identified as a potentially important technology for future massively parallel-computing systems. The development of optoelectronic smart pixels based on InGaAs/AlGaAs multiple-quantum-well modulators and detectors flip-chip solder-bump bonded onto complementary-metal-oxide-semiconductor (CMOS) circuits and the design and construction of an experimental processor in which the devices are linked by free-space optical interconnects are described. For demonstrating the capabilities of the technology, a parallel data-sorting system has been identified as an effective demonstrator. By use of Batcher's bitonic sorting algorithm and exploitation of a perfect-shuffle optical interconnection, the system has the potential to perform a full sort on 1024, 16-bit words in less than 16 mus. We describe the design, testing, and characterization of the smart-pixel devices and free-space optical components. InGaAs-CMOS smart-pixel, chip-to-chip communication has been demonstrated at 50 Mbits/s. It is shown that the initial system specifications can be met by the component technologies.

A parallel optical implementation of arithmetic operations

“…This eliminates the need for complex operations like Perfect Shuffle [24,70,71] to combine input planes, which is necessary for stateless planes since in techniques like optical shadow casting, optical logic gates or symbolic substitution corresponding bits should be spatially adjacent.…”

An intra-chip free-space optical interconnect

“…There are also discussions of how free-space optics can serve as a part of the global backbone of a packet-switched interconnect [47] or as an inter-chip communication mechanism (e.g., [48]). On the integration side, leveraging 3D integration to build on-chip optoelectronic circuit has also been mentioned as an elegant solution to address various integra-tion issues [49].…”

Rationale and challenges for optical interconnects to electronic chips

“…This has been considered by various authors as part of their analyses [8]- [11], [19]- [21], [26], [29], [30], [47], [58], [101]- [104]. We discuss some of the challenges in receiver design in Section III-A1.…”

“…They have successfully been made in large arrays that have also been solder bonded to the circuits. Their performance has been good enough to allow demonstration of large optically interconnected laboratory systems (see, e.g., [42], [48], [58], and [113]). When integrated with CMOS, the quantum-well technology is sometimes described as CMOS-SEED or optoelectronic VLSI.…”