Organic Computing at the System on Chip Level

Bouajila, Abdelmajid; Zeppenfeld, Johannes; Stechele, Walter; Herkersdorf, Andreas; Bernauer, Andreas; Bringmann, Oliver

doi:10.1109/vlsisoc.2006.313257

Cited by 24 publications

(10 citation statements)

References 6 publications

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“…Their paper proposes a concept that applies autonomic or organic computing principles to hardware designs. An implementation of a processing pipeline of a single RISC CPU core using these principles is discussed by Bouajila et al [1]. The SDVM R instead is a software-realization on top of processing elements using these autonomous principles to create a virtualization layer for FPGAs.…”

Section: Related Workmentioning

confidence: 99%

SDVM<sup>R</sup> – managing heterogeneity in space and time on multicore SoCs

Hofmann

Waldschmidt

Haase

2010

2010 NASA/ESA Conference on Adaptive Hardware and Systems

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The dynamic reconfiguration of recent FPGAs offers an important step to adaptive behavior of Systems-onChip (SoCs). These dynamically reconfigurable systems add another degree of freedom to the design space. When a processing element gets reconfigured using one with a different architecture, heterogeneity spans the temporal dimension, too. Now, the question arises how could this type of heterogeneity be managed at run time.This paper analyzes the challenges of such an adaptive SoC. We show that many of the requirements for an FPGA-based realization are met by the SDVM, the Scalable Dataflow-driven Virtual Machine which has been successfully implemented and tested on a cluster of workstations. Focusing on run time reconfiguration, the SDVM has evolved to a virtualization layer for multicore systems based on FPGAs, now called SDVM R . This virtualization layer allows for a transparent run time reconfiguration of the underlying hardware reducing the complexity of the system's temporal heterogeneity as seen by the application.

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Section: Related Workmentioning

confidence: 99%

SDVM<sup>R</sup> – managing heterogeneity in space and time on multicore SoCs

Hofmann

Waldschmidt

Haase

2010

2010 NASA/ESA Conference on Adaptive Hardware and Systems

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“…In order to minimize the error recovery overhead, a new customized micro-rollback [29] is presented. As the shadow register technique has an error detection latency of only one clock cycle, storing the last state in history registers (figure 1) is sufficient to perform a micro-rollback [30].…”

Section: Related Workmentioning

confidence: 99%

A rapid prototyping system for error-resilient multi-processor systems-on-chip

May

Wehn

Bouajila

et al. 2010

2010 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE 2010)

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Abstract-Static and dynamic variations, which have negative impact on the reliability of microelectronic systems, increase with smaller CMOS technology. Thus, further downscaling is only profitable if the costs in terms of area, energy and delay for reliability keep within limits. Therefore, the traditional worst case design methodology will become infeasible. Future architectures have to be error resilient, i.e., the hardware architecture has to tolerate autonomously transient errors.In this paper, we present an FPGA based rapid prototyping system for multi-processor systems-on-chip composed of autonomous hardware units for error-resilient processing and interconnect. This platform allows the fast architectural exploration of various error protection techniques under different failure rates on the microarchitectural level while keeping track of the system behavior. We demonstrate its applicability on a concrete wireless communication system.

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“…Although this approach has only been proposed for certain types of image processing algorithms, the idea that processors change their behavior based on incoming data that also may include instructions to perform based on the local state of a processor is the work that could be considered most closely related to our ideas on invasive computing. Self-organization is also a major topic in organic computing, e.g., [14], [15]. In the context of multi-threaded architectures, CAPSULE [16] has split/spawn mechanisms.…”

Section: Related Workmentioning

confidence: 99%

FSM-controlled architectures for linear invasion

Arifin

Membarth

Amouri

et al. 2009

2009 17th IFIP International Conference on Very Large Scale Integration (VLSI-SoC)

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Abstract-Invasive computing is a novel concept in multiprocessor architecture and programming. Invasion will become an important step towards self-organizing behavior which will be needed in the next generation of massively parallel MPSoCs with unrivaled performance and resource efficiency numbers as one of the main challenges for MPSoC apart from their programming. In this paper we introduce and model a finite state machine for controlling the invasive process in different architectural granularities. The applicability of our FSM is tested in case studies for a reconfigurable MPSoC platform and a fine-grained platform. The results show substantial flexibility gains with only marginal additional hardware cost.

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Organic Computing at the System on Chip Level

Cited by 24 publications

References 6 publications

SDVM<sup>R</sup> – managing heterogeneity in space and time on multicore SoCs

SDVM<sup>R</sup> – managing heterogeneity in space and time on multicore SoCs

A rapid prototyping system for error-resilient multi-processor systems-on-chip

FSM-controlled architectures for linear invasion

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Organic Computing at the System on Chip Level

Cited by 24 publications

References 6 publications

SDVM<sup>R</sup> &#x2013; managing heterogeneity in space and time on multicore SoCs

SDVM<sup>R</sup> &#x2013; managing heterogeneity in space and time on multicore SoCs

A rapid prototyping system for error-resilient multi-processor systems-on-chip

FSM-controlled architectures for linear invasion

Contact Info

Product

Resources

About

SDVM<sup>R</sup> – managing heterogeneity in space and time on multicore SoCs

SDVM<sup>R</sup> – managing heterogeneity in space and time on multicore SoCs