Organization of shared memory with synchronization for multiprocessor-on-a-chip

Abstract

The TSVM is a logical structured memory with a synchronization to improve a performance in a multi-threaded parallel processing. The physical TSVM is realized by the TSVM cache (TC) and a conventional memory in a Multiprocessor-on-a-chip (MOC) system. The L1 cache in a CPU consists of the TC, the General variable cache (GVC), and the instruction cache. The IYA (IY architecture) that is a new architecture divides a conventional data cache into the TC and GVC. The TC caches the shared variables with a synchronization, and the GVC caches other general variables. Regardless of a CPU core, a MOC with the IYA can utilize parallelisms from the instruction level and the statement level to the thread level systematically. To estimate the effect of the TC, preliminary experiments are performed on the multi-chip multiprocessor including the stand-alone TSVM. The result shows that the TSVM cache improves the performance.

Coherence Maintenances to realize an efficient parallel processing for a Cache Memory with Synchronization on a Chip-Multiprocessor

“…We have proposed the shared memory organization constructed by the TSVM cache and structure on the conventional memory, and we have estimated the performance of the TSVM cache using a hardware emulator with a standalone TSVM [17]. Also, in the same environment, we have estimated the effects of the dedicated shared bus for coherence maintenance, the distribution as cache and the relaxed load/store instructions.…”

“…In general, a synchronization is performed apart from communication. We have proposed a shared variable with synchronization, TSVM (Tagged Shared Variable Memory) [17], which combines communication with synchronization to realize more efficient parallel processing. The TSVM can implement the conditional synchronization, mutual exclusion and barrier synchronization easily and systematically.…”