Origin, control and elimination of undercut in silicon deep plasma etching in the cryogenic process

Boufnichel, Mohamed; Lefaucheux, Philippe; Aachboun, S.; Dussart, Rémi; Ranson, P.

doi:10.1016/j.mee.2004.12.002

Cited by 55 publications

(44 citation statements)

References 18 publications

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“…It might be possible that etching at deeper, cryogenic temperatures (lower than À100 C) could be a solution to that problem, since the substrate temperature is known to be a critical parameter for the formation and stability of SiO x F y passivation layers. 31,49 Although recently published work in the cryogenic etch regime did not yield nanostructures with shorter correlation lengths than in this work, further optimization of process parameters in this regime could successfully close the gap to structures with higher aspect ratios at low correlation lengths. 15 In general, Black Silicon fabrication via reactive ion etching has proven to be astonishingly robust regarding substrate temperature variation.…”

Section: -9mentioning

confidence: 58%

“…Thus, a high O 2 content results in a high passivation component in the plasma that hinders the silicon etching reaction. 31 As a consequence, both L C and structure depth are lowered in high oxygen plasmas. Otherwise, high SF 6 plasmas possess a high etching capability and hence provide Black Silicon nanostructures with raised geometrical dimensions and, eventually, even give rise to frayed structures due to undesired sidewall pore etching.…”

Section: A Structure Evolution During Etchingmentioning

confidence: 99%

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The structural and optical properties of black silicon by inductively coupled plasma reactive ion etching

Steglich

Käsebier

Zilk

et al. 2014

Journal of Applied Physics

114

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Black Silicon nanostructures are fabricated by Inductively Coupled Plasma Reactive Ion Etching (ICP-RIE) in a gas mixture of SF6 and O2 at non-cryogenic temperatures. The structure evolution and the dependency of final structure geometry on the main processing parameters gas composition and working pressure are investigated and explained comprehensively. The optical properties of the produced Black Silicon structures, a distinct antireflection and light trapping effect, are resolved by optical spectroscopy and conclusively illustrated by optical simulations of accurate models of the real nanostructures. By that the structure sidewall roughness is found to be critical for an elevated reflectance of Black Silicon resulting from non-optimized etching processes. By analysis of a multitude of structures fabricated under different conditions, approximate limits for the range of feasible nanostructure geometries are derived. Finally, the technological applicability of Black Silicon fabrication by ICP-RIE is discussed

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Section: -9mentioning

confidence: 58%

Section: A Structure Evolution During Etchingmentioning

confidence: 99%

The structural and optical properties of black silicon by inductively coupled plasma reactive ion etching

Steglich

Käsebier

Zilk

et al. 2014

Journal of Applied Physics

114

View full text Add to dashboard Cite

show abstract

“…Ion trajectories affected by electrostatic charging of the mask have been discussed in the literature and are not believed to contribute significantly to ion flux in the areas shadowed by the mask. 15 Much evidence indicates that the observed roughness is caused by a passivation layer that gradually builds up during the etch process. However, this layer does not reduce the overall etch rate significantly.…”

Section: Discussionmentioning

confidence: 99%

Study of the Roughness in a Photoresist Masked, Isotropic, SF[sub 6]-Based ICP Silicon Etch

Larsen¹,

Petersen²,

Hansen

2006

J. Electrochem. Soc.

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In this paper we study the etching behavior and the resulting roughness in photoresist-masked isotropic silicon plasma etch performed in an inductively coupled plasma ͑ICP͒ etcher using SF 6 . We report detailed observations of the resulting roughness for various etching parameters, covering: pressure from 2.5 to 70 mTorr, SF 6 flow rate from 50 to 300 sccm, platen power from 0 to 16 W, and ICP power from 1000 to 3000 W. Etch processes with a normalized roughness below 0.005 were found at low pressure, p = 10 mTorr, while larger normalized roughness, above 0.02, occurred at higher pressures, p = 40-70 mTorr. Here the normalized roughness is the ratio of the roughness amplitude to the etch depth. The rough etching processes showed characteristic high-aspect-ratio and crystal-orientation-dependent surface morphology. The temporal evolution of this roughness was studied, and observations suggest a gradual buildup of surface contamination ͑redeposits͒ originating from the photoresist mask. A model was used to analyze the etched profiles with respect the internal etching conditions. The almost isotropic etching profiles, obtained in both rough and smooth etching processes, are generally highly radical-dependent; however, the surface roughness itself can be reduced dramatically using an ion energy above a certain threshold value. The roughness causing mechanism is discussed.

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“…44 Oxidic ALD-deposited hard masks like Al 2 O 3 are reported to have lower pinhole density and thus higher etch selectivity than conventionally deposited etch hard masks.…”

Section: The Passivation Step In Spatial Rie: Ald-based Low-pressurementioning

confidence: 99%

Cyclic Etch/Passivation-Deposition as an All-Spatial Concept toward High-Rate Room Temperature Atomic Layer Etching

Roozeboom

Bruele

Creyghton

et al. 2015

ECS J. Solid State Sci. Technol.

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Conventional (3D) etching in silicon is often based on the 'Bosch' plasma etch with alternating half-cycles of a directional Sietch and a fluorocarbon polymer passivation. Also shallow feature etching is often based on cycled processing. Likewise, ALD is time-multiplexed, with the extra benefit of half-reactions being self-limiting, thus enabling layer-by-layer growth in a cyclic process. To speed up growth rate, spatial ALD has been successfully commercialized for large-scale and high-rate deposition at atmospheric pressure. We conceived a similar spatially-divided etch concept for (high-rate) Atomic Layer Etching (ALEt). The process is converted from time-divided into spatially-divided by inserting inert gas-bearing 'curtains' that confine the reactive gases to individual injection slots in a gas injector head. By reciprocating substrates back and forth under such head one can realize the alternate etching/passivation-deposition cycles at optimized local pressures, without idle times needed for switching pressure or purging. Another improvement toward an all-spatial approach is the use of ALD-based oxide (Al 2 O 3 , SiO 2 , etc.) as passivation during, or gap-fill after etching. This approach, called spatial ALD-enabled RIE, has industrial potential in cost-effective back-endof-line and front-end-of-line processing, especially in patterning structures requiring minimum interface, line edge and fin sidewall roughness (i.e., atomic-scale fidelity with selective removal of atoms and retention of sharp corners). Today, the continuous doubling of the transistor count on planar microprocessor and memory chips in a two-year cadence has reached the point where Moore's Law (essentially an economic law) and Dennard's scaling (transistor and pitch dimensions) have approached their limits in 2D-scaling. The end of the planar device era was marked with the introduction in 2011 of the 22-nm Tri-Gate device.1,2 Figure 1 shows its design with gates surrounding the channel on three sides of vertical fins to improve gate delay.Today, at the emergence of the 10-nm technology node and the 50 th anniversary of Moore's Law, 3D device and integration solutions are being rapidly introduced both intra-chip, e.g., Gate-All-Around, 3 vertical NAND, 4 and inter-chip, e.g., 3D Through-Silicon Vias (TSVs). 5History of 3D etching.-Whereas the transistor design has been planar for most of its history, its periphery has been subjected to 3D design early on. One of the earliest 3D concepts has been the basic invention of 3D TSVs, already filed in 1958 by the famous W. Shockley, 6 cf. Fig. 2. Yet, in reality 3D Through-Silicon Via (TSV) technology took decades to accelerate the now rapidly growing stacked-chips and micro-electromechanical systems (MEMS) markets by enabling their interconnection in a 3D-integrated System-in-Package (i.e. the so-called 'More than Moore' domain). Today, the mainstream industrial technology for etching of both TSV and MEMS structures is ion-assisted etching or (Deep) Reactive Ion Etching. This method has become so ...

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Origin, control and elimination of undercut in silicon deep plasma etching in the cryogenic process

Cited by 55 publications

References 18 publications

The structural and optical properties of black silicon by inductively coupled plasma reactive ion etching

The structural and optical properties of black silicon by inductively coupled plasma reactive ion etching

Study of the Roughness in a Photoresist Masked, Isotropic, SF[sub 6]-Based ICP Silicon Etch

Cyclic Etch/Passivation-Deposition as an All-Spatial Concept toward High-Rate Room Temperature Atomic Layer Etching

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