Origin of Negative Capacitance Transient in Ultrascaled Multidomain Metal-Ferroelectric-Metal Stack and Hysteresis-Free Landau Transistor

Singh, Khoirom Johnson; Bulusu, Anand; Dasgupta, S.

doi:10.1109/ted.2021.3139057

Cited by 6 publications

(1 citation statement)

References 32 publications

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“…Due to the lack of a path to the substrate side when using Silicon on Insulator (SOI) wafers, several papers investigated to solve MOSFET difficulties such as parasitic capacitance and short channel effects will reduce the thermal conductivity of the structure [11][12][13][14][15][16]. Junctionless FETs (JL-FETs) are extensively doped devices with no difference in active region doping, as a result, the current flow mechanism differs from that of MOSFETs without junctions, and the fabrication procedure will be simple [17][18][19][20][21][22][23][24][25][26][27][28][29][30].…”

Section: Introductionmentioning

confidence: 99%

Performance improvement of junctionless SOI-MOSFETs by a superior depletion technique

Abrishami,

Orouji,

Madadi

2023

Phys. Scr.

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This work uses a superior depletion technique to present a junctionless silicon-on-insulator (SOI) metal-oxide field-effect transistor (MOSFET) in a 14 nm regime. The suggested technique embeds a P-type area into the buried silicon oxide (SiO2) layer. The p-silicon area has several effects on the proposed structure (EPB-JLSM): First, it helps us attain a full depletion area in the channel. Second, the self-heating improves due to the higher thermal conductivity of silicon than the silicon nitride. Finally, the embedded area causes the lower hole concentration (high Vds at accumulation mode), resulting in a better kink effect. Also, we discuss the impact of inserting the P-silicon area geometry into the buried layer on the DC performance device, such as height and thickness. The P-silicon area decreases the leakage current (IOFF) by three orders of magnitude (∼1000%), and also slightly enhances the drive current (ION) (∼20%), and reduces subthreshold swing (SS) from 186 to 109 mV dec−1 (∼71%) compared to a typical junctionless SOI MOSFET (C-JLSM). Furthermore, we discuss the effect of the buried region and gate insulator materials on the proposed device’s performance.

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