OUM - A 180 nm nonvolatile memory cell element technology for stand alone and embedded applications

Lai, Sheng-Chih; Lowrey, T.

doi:10.1109/iedm.2001.979636

Cited by 237 publications

(162 citation statements)

References 1 publication

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“…5,[7][8][9][10] The realization of PRAM devices is, however, still limited due to the requirements of small cell size, high scalability, and low power consumption. The major bottleneck for achieving high density PRAM devices is the large writing currents needed to prepare the system in the amorphous physical state associated with high resistance ͑reset state͒.…”

mentioning

confidence: 99%

Size-dependent phase transition memory switching behavior and low writing currents in GeTe nanowires

Lee

Jung

et al. 2006

Applied Physics Letters

123

149

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Synthesis and device characteristics of highly scalable GeTe nanowire-based phase transition memory are reported. The authors have demonstrated reversible phase transition memory switching behavior in GeTe nanowires, and obtained critical device parameters, such as write and erase currents, threshold voltage, and programming curves. The diameter dependence of memory switching behavior in GeTe nanowires was studied and a systematic reduction of writing currents with decreasing diameter was observed, with currents as low as 0.42mA for a 28nm nanowire. Results show that nanowires are very promising for scalable memory applications and for studying size-dependent phase transition mechanisms at the nanoscale.

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mentioning

confidence: 99%

Size-dependent phase transition memory switching behavior and low writing currents in GeTe nanowires

Lee

Jung

et al. 2006

Applied Physics Letters

123

149

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“…30 The chalcogenide material can exist in two different phases: a low-resistive, ordered, polycrystalline configuration and a high-resistive, disordered, amorphous configuration. [29], a diode has been embedded in the resistive memory element in oder to introduce a rectifying behavior.…”

Section: Programmable Partmentioning

confidence: 99%

Silicon Nanowire Arrays and Crossbars: Top-Down Fabrication Techniques and Circuit Applications

Ben-Jamaa¹,

Gaillardon²,

Clermidy³

et al. 2011

sci adv mat

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Several nanowire technologies have emerged recently, providing a way to continue the scaling down of complementary metal-oxide-semiconductor (CMOS) technology. The opportunities offered at the level of logic circuit design depend on the technology properties, and some applications seem to be suitable for specific technologies. In this paper, we survey three nanowire technologies that yield nanowire arrays. All of them depend on the photolithography limit but they differ with respect to the processing and the device properties. We show the ability of the spacer technique to yield nanowires with a pitch below the photolithography limit. We introduce the nanowire crossbars in a pure CMOS process and extract the parasitics that affect nanowire crossbar circuits. Vertically stacked nanowires are also demonstrated with the deep reactive ion etching (DRIE) process. We link the surveyed processes to specific circuit architectures that are optimized for the considered technologies. A nanowire decoder for sub-lithographic nanowires is demonstrated with the smallest size compared to other competing technologies. Then an optimized crossbar multiplexer is presented, which takes into account the presence of parasitics. Finally, a general library of logic gates based on vertically stacked nanowires is evaluated showing a smaller area and a better performance than CMOS.

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“…It has many features such as high speed, small cell size, good cycle ability, low power consumption, low cost and good compatibility with standard CMOS processes [2,3,4]. Specifically, when a phase change material is heated to a high temperature with a long-pulse current, it crystallizes and reduces its resistance as SET operation.…”

Section: Introductionmentioning

confidence: 99%

A smart method of optimizing the read/write current on PCM array

Zhang

Chen

Zhang

et al. 2014

IEICE Electron. Express

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A method for optimizing the read/write current on phase change memory array is proposed. A smart current adjustment circuit is designed to bi-directionally alter the internal read/write current. The best read/write condition based on arrays can be found through this adjustment approach. Example of a 2-dimensional shmoo test on a 16k-bit phase change array implemented in 0.13 µm CMOS technology is given. The resistance distribution can also be roughly obtained. This method, taking advantage of the peripheral circuit, provides statistical yield data on a variety of read/write current, thus offering reliable and helpful indicators for chip parameter setup and process optimization.

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OUM - A 180 nm nonvolatile memory cell element technology for stand alone and embedded applications

Cited by 237 publications

References 1 publication

Size-dependent phase transition memory switching behavior and low writing currents in GeTe nanowires

Size-dependent phase transition memory switching behavior and low writing currents in GeTe nanowires

Silicon Nanowire Arrays and Crossbars: Top-Down Fabrication Techniques and Circuit Applications

A smart method of optimizing the read/write current on PCM array

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