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This paper discusses the development status of ovonic unified memory (OUM), a phase-change, nonvolatile semiconductor memory technology for VLSI stand-alone memory and embedded applications. A 4Mb VLSI test memory is used as a development vehicle with 0.18µm 3V CMOS. Characterization of the OUM technology is reviewed for high density, low voltage, high cyclecount nonvolatile memory applications with short programming times. OUM offers advantages in cell size, process complexity, cost, write times, cycling, cell energy consumption during write and direct over-write.Data storage is accomplished in an OUM cell by a thermallyinduced phase change between amorphous and polycrystalline states in a thin film of chalcogenide alloy similar to the materials used in rewriteable CD and DVD optical disks. This rapid reversible structural change in the Ge x Sb y Te z alloy film results in a change in material resistivity that is measured during the read operation. OUM technology uses a short electrical pulse to achieve the amorphous state (high-resistance RESET state) and lower but a bit longer current pulse to convert to the polycrystalline state (lower-resistance SET state). The portion of the alloy film near a bottom resistive electrode changes state as a result of joule heating during the programming pulse [1]. Because of the small programmable volume of the film, the programming energy is small -suitable for portable communication applications. Figure 12.4.1 shows multiple oscilloscope traces of the cycling characteristics of the OUM memory cell element. Each trace is a series of 4 sequential operations, write/read/writecomplement/read, cycling at 5MHz. An 8ns reset pulse is applied with a ~5ns falling edge. The subsequent read shows 85kΩ programmed resistance. Next application of a set pulse of 85ns results in a resistance of 2kΩ. The beginning of the set pulse shows the device threshold voltage, Vth, to be ~0.6V. The maximum device voltage required for memory operation occurs during the reset programming pulse, which is <0.8V. The plot shows the superposition of 21 separate scope traces taken throughout 2E8 cycles at logarithmic time intervals.With 0.18µm lithography, a maximum device voltage of 0.8V and a diode voltage drop of 0.8-0.9V during the RESET operation allow 1.0V for CMOS control circuitry in a 3V CMOS operation. This avoids the high-voltage transistors needed in Flash and other nonvolatile memories under development. OUM memory is seamlessly embedded in a logic process by using low temperature OUM memory process modules after transistor formation. Figure 12.4.2 shows I-V characteristics of the chalcogenide memory element for both the SET and RESET states. When a voltage above Vth is applied to a device in the RESET state, the device switches electronically to a low-resistance dynamic state, permitting low-voltage programming. The figure also shows a significant separation between the read current and set/reset currents, allowing disturb-free read. Figure 12.4.3 shows the read resistance of the cell as a conse...