Out-of-order instruction fetch using multiple sequencers

Oberoi, Paramjit S.; Sohi, Gurindar S.

doi:10.1109/icpp.2002.1040855

Cited by 6 publications

(4 citation statements)

References 33 publications

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“…Some architectural optimizations can solve such problem. For example, trace cache caches traces of the dynamic instruction stream, so instructions that are otherwise noncontiguous appear contiguous [20] . Identification of this pattern demonstrates the value of trace cache to processor designer, especially for the scenario of Java workloads optimization with many dynamically invoked methods.…”

Section: A Performance Analysis and Optimizationmentioning

confidence: 99%

Frequent Instruction Sequential Pattern Mining in Hardware Sample Data

Zou

Xiao

Hou

et al. 2010

2010 IEEE International Conference on Data Mining

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When parallelism and heterogeneity has become the trend for computer system design, both the size and the complexity of the hardware sample data generated by Performance Monitoring Unit (PMU) increase fast, thus automatic analysis methods, i.e. data mining methods, are urgently needed to accelerate hardware sample data analysis. We are the first to study instruction sequential pattern mining for hardware sample data. It is a challenging task due to the implicit sequential relationship contained in the data and due to the importance of low frequency patterns. As a solution, we i) provide a novel algorithm ProfSpan; ii) adapt two existing algorithms, which are based on candidate generation and projected database generation, to hardware sample data. Our evaluation results show ProfSpan can reduce up to 75% and 80% of execution time compared with other two algorithms. Particularly, up to 50% of frequent patterns mined by ProfSpan in hardware sample data are crossing basic block boundaries and can not be found by existing methods for source code or disassembly code. We also analyze three example patterns identified by ProfSpan: consecutive loads, JIT entry sequence, and conditional code dependency sequence, to illustrate how ProfSpan can benefit performance analysis. Finally, we apply patterns to module classification and obtain promising results.

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Section: A Performance Analysis and Optimizationmentioning

confidence: 99%

Frequent Instruction Sequential Pattern Mining in Hardware Sample Data

Zou

Xiao

Hou

et al. 2010

2010 IEEE International Conference on Data Mining

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“…The required instructions are extracted from the fetched cache lines, and the output from the fetch unit is a block of instructions in program order. Figure 1 illustrates a parallel fetch unit based on the design we proposed earlier [13]. We refer the reader to the original paper for a complete description, but a short overview of the design follows.…”

Section: Parallel Fetch Using Multiple Sequencersmentioning

confidence: 99%

“…If the same fragment is encountered again before its buffer has been reallocated, the instructions are reused instead of being fetched again from the instruction cache. Depending on the benchmark, 20-70% of fragments can be reused with just 16 fragment buffers [13].…”

Section: Fragment Buffersmentioning

confidence: 99%

Parallelism in the front-end

Oberoi

Sohi

2003

SIGARCH Comput. Archit. News

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As processor back-ends get more aggressive, front-ends will have to scale as well. Although the back-ends of superscalar processors have continued to become more parallel, the front-ends remain sequential. This paper describes techniques for fetching and renaming multiple non-contiguous portions of the dynamic instruction stream in parallel using multiple fetch and rename units. It demonstrates that parallel front-ends are a viable alternative to high-performance sequential front-ends.Compared with an equivalently-sized trace cache, our technique increases cache bandwidth utilization by 17%, front-end throughput by 20%, and performance by 5%. Parallelism also enhances latency tolerance: a parallel front-end loses only 6% performance as the cache size is decreased from 128 KB to 8 KB, compared with a 50-65% performance loss for sequential fetch mechanisms.

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“…Oberoi and Sohi [15] propose a mechanism for out-oforder fetching in superscalar processors. It uses multiple sequencers that prefetch instructions into a pool of buffers, from which they are taken to rename.…”

Section: Related Workmentioning

confidence: 99%