Over 1 GW/cm₂ Vertical Ga₂O₃ Schottky Barrier Diodes Without Edge Termination

Identification and Suppression of Majority Surface States in the Dry-Etched β-Ga2O3

“…Thus, the surface treatment was reported to suppress these traps for improving the device of β-Ga 2 O 3 SBDs. 2 Figure 2a shows the semilogarithmic J−V of diodes S1−S4. All diodes exhibit high rectification ratios >10 9 at ±2 V. Notably, the oxygen-annealed sample S3 exhibits the lowest reverse leakage current due to the charge compensation effect in a formed ultrathin semi-insulating (SI) surface layer.…”

“…Beta-gallium oxide (β-Ga 2 O 3 ) has attracted extensive efforts in developing high-performance power devices . Dry etching is a crucial fabrication process to define device patterns or remove surface contaminants but in turn inevitably induces surface damages and deteriorates device performance . To overcome this barrier, various surface treatments have been reported, which had substantial impacts on the electrical properties of β-Ga 2 O 3 power diodes. − Notably, the majority traps ( E C –0.75 eV, named E2*) were attributed to an intrinsic defect that has been reported to be related to gallium vacancies (V Ga ) , or divacancy complexes (V Ga –V O ) , in β-Ga 2 O 3 .…”

“…Dry etching is a crucial fabrication process to define device patterns or remove surface contaminants but in turn inevitably induces surface damages and deteriorates device performance . To overcome this barrier, various surface treatments have been reported, which had substantial impacts on the electrical properties of β-Ga 2 O 3 power diodes. − Notably, the majority traps ( E C –0.75 eV, named E2*) were attributed to an intrinsic defect that has been reported to be related to gallium vacancies (V Ga ) , or divacancy complexes (V Ga –V O ) , in β-Ga 2 O 3 . Recently, the E2* trap was also reported as a dominant contributor to limit the Schottky diode performance and as the primary source of the subthreshold instability of β-Ga 2 O 3 MESFETs. − So far, the underlying trap evolution and the associated correlation of carrier transport and surface electronic structures still lack exploration.…”

“…However, the N TE2* of E2* ( E C – 0.75 eV, σ E2* = 1.12 × 10 –14 cm 2 ) was enhanced by the dry etching. Thus, the surface treatment was reported to suppress these traps for improving the device of β-Ga 2 O 3 SBDs …”

“…The 1/ C 2 slope difference results from the charge density variation of surface states in the UID β-Ga 2 O 3 epilayer . In particular, sample S3 exhibits the lowest capacitance corresponding to its minimum leakage current, as the SI interfacial layer contributes an additional capacitance ( C I ) in series with the capacitance ( C L ) of depletion region the β-Ga 2 O 3 epilayer. In terms of 1/ C = 1/ C I + 1/ C L , the SI thickness ( d ) is estimated to be 13 nm, which is exactly equal to the difference of the depletion widths for samples S3 and S4.…”