2015
DOI: 10.7567/jjap.54.04dg06
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Over 10 GHz lateral silicon photodetector fabricated on silicon-on-insulator substrate by CMOS-compatible process

Abstract: We report a design and implementation of lateral silicon photodetectors fabricated on a silicon-on-insulator (SOI) substrate in a complementary CMOS-compatible process. In addition, we disscuss the structure dependences on the frequency and optimum design for a maximum bandwidth. A standard device fabricated with a 210 nm absorbing layer, a finger width of 1.00 µm, a finger spacing of 1.63 µm, a square detector area of 20 × 20 µm2, and a pad size of 60 × 60 µm2 achieved a bandwidth of 12.6 GHz at a bias voltag… Show more

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Cited by 32 publications
(7 citation statements)
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“…In this regards, Si is an excellent photodetector in the 850 nm band with higher responsivity than III-V photodetector. However, longer absorption length, RC time, and transit time in Si considerably limit bandwidth [9][10][11]. The bandwidth limitation of Si photodetector is significantly improved by realizing lateral pin photodetector in a guided wave configuration, particularly in a Silicon-on-Insulator (SOI) platform [12].…”
mentioning
confidence: 99%
“…In this regards, Si is an excellent photodetector in the 850 nm band with higher responsivity than III-V photodetector. However, longer absorption length, RC time, and transit time in Si considerably limit bandwidth [9][10][11]. The bandwidth limitation of Si photodetector is significantly improved by realizing lateral pin photodetector in a guided wave configuration, particularly in a Silicon-on-Insulator (SOI) platform [12].…”
mentioning
confidence: 99%
“…[ 19 ] Conventionally, lateral PIN photodiodes have low capacitance and are suitable for high‐speed applications. In 2015, Li et al [ 20 ] proposed a structure combining the advantages of SOI material and lateral PIN photodiode fabricated in a CMOS‐compatible process, see Figure a. The response time being limited by the transition of carriers and the depletion region capacitance, an optimum design of finger spacing for maximum bandwidth was demonstrated.…”
Section: The Pin Photodiode On Soimentioning
confidence: 99%
“…Figure 1(a) shows the partially-depleted Z 2 -FET structure we use in our simulations, with T Si = 200 nm as in [15], [18] and a p-type doping concentration of 10 15 cm −3 . The front gate length is L G = 0.5 µm and intrinsic length (region not covered by front gate) is L IN = 1.5 µm.…”
Section: A Device Structure and Operating Principlementioning
confidence: 99%
“…Other applications, such as optical communication, image sensing, and photodetection are also widely explored in SOI because of high radiation hardness, as well as compatibility with SOI electronics and photonics [11]- [14]. Thus, photodetectors based on various operation mechanisms, using diodes, transistors and interface coupling effects (ICPDs) have been demonstrated in SOI technology [15]- [18].…”
Section: Introductionmentioning
confidence: 99%