Overcoming Variations in Nanometer-Scale Technologies

Sapatnekar, Sachin S.

doi:10.1109/jetcas.2011.2138250

Cited by 60 publications

(24 citation statements)

References 135 publications

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“…These thermal effects not only degrade performance but can lead to a thermal runaway causing momentary or permanent device failure, 4,[20][21][22][23] if the generated heat is not removed promptly and efficiently. This can be a serious challenge for implementing new applications specially related to implantable advanced healthcare electronics.…”

Section: Introductionmentioning

confidence: 99%

Enhanced cooling in mono-crystalline ultra-thin silicon by embedded micro-air channels

et al. 2015

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In today’s digital world, complementary metal oxide semiconductor (CMOS) technology enabled scaling of bulk mono-crystalline silicon (100) based electronics has resulted in their higher performance but with increased dynamic and off-state power consumption. Such trade-off has caused excessive heat generation which eventually drains the charge of battery in portable devices. The traditional solution utilizing off-chip fans and heat sinks used for heat management make the whole system bulky and less mobile. Here we show, an enhanced cooling phenomenon in ultra-thin (>10 μm) mono-crystalline (100) silicon (detached from bulk substrate) by utilizing deterministic pattern of porous network of vertical “through silicon” micro-air channels that offer remarkable heat and weight management for ultra-mobile electronics, in a cost effective way with 20× reduction in substrate weight and a 12% lower maximum temperature at sustained loads. We also show the effectiveness of this event in functional MOS field effect transistors (MOSFETs) with high-κ/metal gate stacks.

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Section: Introductionmentioning

confidence: 99%

Enhanced cooling in mono-crystalline ultra-thin silicon by embedded micro-air channels

et al. 2015

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“…Process variations refer to the variations in the values of CMOS device parameters, such as the transistor width (W ), effective channel length (L ef f ), and oxide thicknesses (t ox ) [9], that occur during the process of fabrication. Due to process variation, performance-related metrics such as the delay, slew, and power in circuits and architectures are severely affected.…”

Section: B Variation-aware Vlusmentioning

confidence: 99%

Variation-Aware Variable Latency Design

Gupta

Sapatnekar

2014

IEEE Trans. VLSI Syst.

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Abstract-Although typical digital circuits are designed so that the clock period satisfies worst-case path delay constraints, the average input excitation often completes computation in less than a clock cycle. Variable latency units (VLUs) allow for improved throughput by allowing one clock cycle for some computations, and two clock cycles for others, using hold logic to differentiate between the two cases. However, they may experience significant throughput losses due to the effects of process variations. We develop a combined presilicon-postsilicon technique for variation-aware VLU design that ensures high throughputs across all manufactured chips. We achieve this by identifying path clusters at the presilicon stage, such that each element of a path cluster is likely to be similarly critical in a manufactured part. We use sensors to determine which path clusters is critical at the postsilicon stage and then activate the appropriate hold logics. Practically, for a small number of path clusters, significant improvements in throughput are achievable. On a set of 32nm PTM-based ISCAS89 circuits, our scheme offers 15.1% throughput enhancements with only 3.3% area overhead.

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“…In this paper, we consider the performance of this associative memory when implemented on unreliable hardware. Considering unreliable hardware is motivated by the fact that, as the feature size of integrated circuits decreases, it is becoming increasingly hard to control the variability associated both with the fabrication process and with the circuit's operating conditions [8,9]. As a result, larger safety margins must be used to maintain yield and performance guarantees.…”

Section: Introductionmentioning

confidence: 99%

Cluster-based associative memories built from unreliable storage

Leduc-Primeau¹,

Gripon²,

Rabbat³

et al. 2014

2014 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP)

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We consider associative memories based on clustered graphs that were recently introduced. These memories are almost optimal in terms of the amount of storage they require (efficiency), and allow retrieving messages with low complexity. We study an unreliable implementation of the memory and compare its error rate and storage efficiency with that of a reliable implementation. We present analytical and simulation results that indicate that the proposed memory structure can tolerate a large number of faults at a reasonable cost, thereby making it a good candidate for achieving highly efficient circuit implementations of associative memories.

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Overcoming Variations in Nanometer-Scale Technologies

Cited by 60 publications

References 135 publications

Enhanced cooling in mono-crystalline ultra-thin silicon by embedded micro-air channels

Enhanced cooling in mono-crystalline ultra-thin silicon by embedded micro-air channels

Variation-Aware Variable Latency Design

Cluster-based associative memories built from unreliable storage

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