Overhead and reliability analysis of algorithm-based fault tolerance in FPGA systems

Jacobs, Adam; Cieslewski, Grzegorz; George, Alan

doi:10.1109/fpl.2012.6339222

Cited by 14 publications

(7 citation statements)

References 11 publications

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“…Jacobs et al implemented algorithmic protection of several matrix multiplication architectures [5]. ABFT was called upon for error detection of the same operator in more recent work, with resource reallocation performed using additional logic [2] and dynamic partial reconfiguration [3] in order to avoid faulty components at runtime.…”

Section: Application-level Fault Tolerancementioning

confidence: 99%

Reduced-precision Algorithm-based Fault Tolerance for FPGA-implemented Accelerators

Davis

Cheung

2016

Lecture Notes in Computer Science

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Abstract. As the threat of fault susceptibility caused by mechanisms including variation and degradation increases, engineers must give growing consideration to error detection and correction. While the use of common fault tolerance strategies frequently causes the incursion of significant overheads in area, performance and/or power consumption, options exist that buck these trends. In particular, algorithm-based fault tolerance embodies a proven family of low-overhead error mitigation techniques able to be built upon to create self-verifying circuitry. In this paper, we present our research into the application of algorithmbased fault tolerance (ABFT) in FPGA-implemented accelerators at reduced levels of precision. This allows for the introduction of a previously unexplored tradeoff: sacrificing the observability of faults associated with low-magnitude errors for gains in area, performance and efficiency by reducing the bit-widths of logic used for error detection. We describe the implementation of a novel checksum truncation technique, analysing its effects upon overheads and allowed error. Our findings include that bitwidth reduction of ABFT circuitry within a fault-tolerant accelerator used for multiplying pairs of 32 × 32 matrices resulted in the reduction of incurred area overhead by 16.7% and recovery of 8.27% of timing model fmax. These came at the cost of introducing average and maximum absolute output errors of 0.430% and 0.927%, respectively, of the maximum absolute output value under transient fault injection.

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Section: Application-level Fault Tolerancementioning

confidence: 99%

Reduced-precision Algorithm-based Fault Tolerance for FPGA-implemented Accelerators

Davis

Cheung

2016

Lecture Notes in Computer Science

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“…ABFT is used to implement fault tolerant matrix operations. Recently, Jacobs et al investigated in [Jacobs et al 2012a] the overhead and reliability of ABFT in FPGA systems. The authors use a Multiply and Accumulate (MAC) unit where the inputs are fed from Block RAM and where the output data is written back to Block RAM.…”

Section: Information Redundancymentioning

confidence: 99%

“…The static area is hardened against SEUs by applying TMR to the netlist of the design. The researchers also investigated the suitability of ABFT for such systems [Jacobs et al 2012a] and presented their own fault injection system [Cieslewski et al 2010].…”

Section: Reconfigurable System On Chipmentioning

confidence: 99%

Mitigation of Radiation Effects in SRAM-Based FPGAs for Space Applications

Siegle

Vladimirova

Ilstad³

et al. 2015

ACM Comput. Surv.

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The use of static random access memory (SRAM)-based field programmable gate arrays (FPGAs) in harsh radiation environments has grown in recent years. These types of programmable devices require special mitigation techniques targeting the configuration memory, the user logic, and the embedded RAM blocks. This article provides a comprehensive survey of the literature published in this rich research field during the past 10 years. Furthermore, it can also serve as a tutorial for space engineers, scientists, and decision makers who need an introduction to this topic.

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“…Many linear algebra operations, common in FPGA applications, can be protected with such algorithm-based techniques: examples include matrix operations [8] and Fourier transformations [9]. Recently published work [10] focussed on design vulnerability reduction using ABFT applied to a matrix multiplier on an FPGA. Our previous work [11], meanwhile, used ABFT for error detection in the same operator while adding additional, fixed logic for dynamic resource reallocation to facilitate fault avoidance at runtime.…”

Section: B Algorithm-based Fault Tolerancementioning

confidence: 99%

Achieving low-overhead fault tolerance for parallel accelerators with dynamic partial reconfiguration

Davis

Cheung

2014

2014 24th International Conference on Field Programmable Logic and Applications (FPL)

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Abstract-While allowing for the fabrication of increasingly complex and efficient circuitry, transistor shrinkage and countper-device expansion have major downsides: chiefly increased variation, degradation and fault susceptibility. For this reason, design-time consideration of fault tolerance will have to be given to increasing numbers of electronic systems in the future to ensure yields, reliabilities and lifetimes remain acceptably high. Many commonly implemented operators are suited to modification resulting in datapath error detection capabilities with far lower area requirements. FPGAs are uniquely placed to allow further area savings to be made when incorporating fault avoidance mechanisms thanks to their dynamic reconfigurability.In this paper, we examine the practicalities and costs involved in implementing hardware-software fault tolerance on a test platform: a parallel matrix multiplication accelerator in hardware, with controller in software, running on a Xilinx Zynq system-on-chip. A combination of 'bolt-on' error detection logic and software-triggered routing reconfiguration serve to provide low-overhead datapath fault tolerance at runtime. Rapid yet accurate fault diagnoses along with low hardware (area), software (configuration storage) and performance penalties are achieved.

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Overhead and reliability analysis of algorithm-based fault tolerance in FPGA systems

Cited by 14 publications

References 11 publications

Reduced-precision Algorithm-based Fault Tolerance for FPGA-implemented Accelerators

Reduced-precision Algorithm-based Fault Tolerance for FPGA-implemented Accelerators

Mitigation of Radiation Effects in SRAM-Based FPGAs for Space Applications

Achieving low-overhead fault tolerance for parallel accelerators with dynamic partial reconfiguration

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