Overlay performance in advanced processes

Bornebroek, Frank; Burghoorn, Jaap; Greeneich, James S.; Megens, Henry; Satriasaputra, Danu; Simons, Geert; Stalnaker, Sunny; Koek, B. H.

doi:10.1117/12.389040

Cited by 11 publications

(7 citation statements)

References 5 publications

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“…The signal at this thickness is around 9 to 10%, which is above the threshold value of 6% we mentioned before. This system relies on the diffraction signals from grating-like alignment marks [2]. A typical alignment process consists of pre-alignment, coarse alignment, and fme alignment stages.…”

Section: Direct Imaging Systemmentioning

confidence: 99%

Ultrafast wafer alignment simulation based on thin film theory

Wu¹,

Williams

Kim³

et al. 2002

SPIE Proceedings

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The shrink of semiconductor fabrication ground rule continues to follow Moore's law over the past years. However, at the 100 nfl node, the fabrication cost starts to rise rapidly. This is mainly due to the increase of complexity in the fabrication process, including the use of hard masks, planarization, resolution enhancement techniques, etc. Smaller device sizes require higher alignment tolerances. Also, higher degree of complexity makes alignment detection more difficult. For example, planarization techniques may destroy mark topography; hard masks may optically bury alignment marks; and more film layers makes the alignment signal more susceptible to process variations. Therefore, in order to achieve reliable alignment, it is absolutely critical to develop an accurate and fast simulation software that can characterize alignment performance based on the film stack structure. In this paper, we will demonstrate that we have built an extremely fast alignment signal simulator for both direct imaging and diffractive detection systems based on simple optical theory. We will demonstrate through examples using our advanced DRAM products that it is capable of accurately mapping the multi-dimensional parameter space spanned by various film thickness parameters within a short period of time, which allows both on-the-fly feedback in alignment performance and alignment optimization.

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Section: Direct Imaging Systemmentioning

confidence: 99%

Ultrafast wafer alignment simulation based on thin film theory

Wu¹,

Williams

Kim³

et al. 2002

SPIE Proceedings

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“…In phased introductions, sensor and applications improvements were validated and integrated in production environments, at various customer sites [2,7,9,10,11,13,14,16]. With the knowledge gained from joint development activities on on-product overlay, the increasing importance of synchronizing alignment mark design criteria, with alignment sensor hardware specifics was recognized [3,4,5,6]. Significant steps forward in this field were made, operating within the boundaries of the ATHENA TM sensor [4,6,8,15].…”

Section: Introductionmentioning

confidence: 98%

Integration of a new alignment sensor for advanced technology nodes

Hinnen

Depre²,

Tanaka³

et al. 2007

SPIE Proceedings

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In this paper alignment and overlay results of the advanced technology nodes are presented. These results were obtained on specially generated wafers as well as on regular manufacturing-type wafers. For this purpose, a new alignment sensor was integrated and evaluated in three generations of lithography tools, placed in R&D and mass manufacturing facilities. The capability of the sensor to align on marks with varying layout was evaluated. Long term overlay stability less than 11 nm was obtained on two different mark types: a standard ASML calibration mark and a flexible Toshiba mark design. The ability to align on low-contrast marks was validated by a dedicated experiment: typical alignment repeatability values of ~1 nm (3sigma) on shallow etch depth mark features of 25 nm are obtained for various mark designs, including flexible pitch alignment marks. From these results, design directions for improved mark detect ability were defined. The jointly developed mark designs were validated for their alignment robustness by an evaluation of manufacturing wafer alignment performance. On-product overlay results on manufacturing wafers were measured for three different process layers of the current technology node. The used alignment strategies were based on new mark capture and fine wafer alignment mark designs, thereby making optimal use of the mark design flexibility potential of the alignment sensor. Typical on-product overlay values obtained were less than 17 nm for the Active Area process layer, less than 12 nm for the Gate Conductor process layer, and less than 19 nm for the Metal-1 process layer; after applying batch corrections, as determined on a set of 2 send-ahead wafers. All results are based on full batch readout on an offline metrology tool. By applying optimal batch process corrections for linear terms, typical overlay values range between 10-14 nm, depending on the layer measured. Finally the sensor's infrared wavelengths were used to demonstrate a robust alignment solution for wafers containing a semi-transparent hard-mask layer.

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“…As reported previously, 1,4 it was designed to minimize sensitivity to process effects such as mark asymmetry and variation in mark depth.…”

Section: Introductionmentioning

confidence: 99%

Advances in process overlay: ATHENA alignment system performance on critical process layers

et al. 2002

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The continuing reduction of IC device dimensions puts stringent demands on the corresponding overlay performance. As part of the total overlay budget, the effects of the different process parameters need to be characterized and well understood. In a joint development program between IMEC and ASML, the robustness of different alignment strategies to process parameters has been evaluated using the ATHENA alignment system. This paper looks at both Front-end (Shallow Trench Isolation) and Back-end (W-CMP and copper dual damascene) processing.To investigate the effect of STI processing on alignment marks in Front-end processing an extensive evaluation has been performed in which both mark design and process parameters have been varied. The robustness to typical long term process variation at the STI CMP step in a production environment has also been evaluated.To improve the robustness of alignment marks in Back-end processing, new mark designs have been evaluated. These designs have been evaluated for two different processes. The first uses traditional W-CMP and sputtered aluminum. The second uses copper dual damascene, with layer stacks consisting of both conventional and low-k dielectric materials. This knowledge will be used to generate alignment strategies for future technology nodes.

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Overlay performance in advanced processes

Cited by 11 publications

References 5 publications

Ultrafast wafer alignment simulation based on thin film theory

Ultrafast wafer alignment simulation based on thin film theory

Integration of a new alignment sensor for advanced technology nodes

Advances in process overlay: ATHENA alignment system performance on critical process layers

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