Oversampled pipeline A/D converters with mismatchshaping

Shabra, Ayman; Lee, Hae-Seung; Hernández, Luis

doi:10.1049/el:19980382

Cited by 4 publications

(8 citation statements)

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“…We first review representative prior techniques to achieve high precision in CMOS pipelined ADCs [3]- [5]. Those are methods to eliminate bit-block gain and offset errors, which arise mainly from capacitor mismatches.…”

Section: The Passive Capacitor Error-averaging Methodsmentioning

confidence: 99%

“…The oversampling method proposed in [5] and [6] produces gain and offset errors of equal amounts but opposite polarities in a similar way as in a logic operation. Input differential signals at the input of a bit-block are exchanged by using analog switches, and the multiplication of minus one to the output digital data from a bit-block is done in alternate clock periods.…”

Section: The Oversampling Methodsmentioning

confidence: 99%

“…On the other hand, in the oversampling method shown in [5], the exchange of the differential input signal and multiplication to the output digital data in digital form are done at every clock to realize the equivalent exchange-capacitor function. This suggests that the digital function helps the analog function reach a minimum and improves the ADC's performance.…”

Section: Introductionmentioning

confidence: 99%

“…This suggests that the digital function helps the analog function reach a minimum and improves the ADC's performance. However, this method is not applicable to ADCs with a 1.5-bit bit-block architecture, which is commonly used in the CMOS pipelined ADC, because the error in the bit-block in [5] is restricted to the form of even function.…”

Section: Introductionmentioning

confidence: 99%

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A Digitally Assisted Gain and Offset Error Cancellation Technique for a CMOS Pipelined ADC with a 1.5-bit Bit-Block Architecture

Tanaka¹,

Sugimoto²

2007

IEICE Transactions on Fundamentals of Electronics, Communicatio

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This paper proposes a very simple method of eliminating the gain and offset errors caused by mismatches of elements, such as capacitors, for a high-speed CMOS pipelined ADC with a 1.5-bit architecture. The gain and offset errors in a bit-block due to capacitor mismatch are analog-to-digital (A-D) converted without correcting errors, but by exchanging capacitors at every clock. The obtained results are digital codes at the output of the ADC, and they contain positive and negative errors in turn. The two consecutive codes are then added in digital form, thus canceling the errors. This results in the twofold oversampling operation. As the distortion component arises when the input signal frequency increases, a frontend SHA is used to completely eliminate distortion up to the Nyquist frequency. The behavioral simulation of a 14-bit ADC reveals that this CMOS pipelined ADC with a 1.5-bit bit-block architecture, even without a frontend SHA, has more than 70 dB of spurious-free dynamic range (SFDR) for up to an 8 MHz input signal when each of the upper three bit-blocks has gain and offset errors of +0.8% when the clock frequency is 102.4 MHz. Using an SHA in front further improves the SFDR to 95 dB up to the signal frequency bandwidth of 25.6 MHz.

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Section: The Passive Capacitor Error-averaging Methodsmentioning

confidence: 99%

Section: The Oversampling Methodsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

A Digitally Assisted Gain and Offset Error Cancellation Technique for a CMOS Pipelined ADC with a 1.5-bit Bit-Block Architecture

Tanaka¹,

Sugimoto²

2007

IEICE Transactions on Fundamentals of Electronics, Communicatio

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“…This work investigates the use of pipeline ADCs under these low oversampling conditions. In particular, it develops mismatch shaping (MS) algorithms for pipeline converters [1], [2]. MS, a technique developed for delta-sigma converters [3], pushes the distortion introduced by component mismatch Manuscript out of the signal band, thereby improving the linearity.…”

Section: Introductionmentioning

confidence: 99%

Oversampled pipeline A/D converters with mismatch shaping

Shabra

Lee

2002

IEEE J. Solid-State Circuits

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This paper presents a pipeline analog-to-digital converter (ADC) with improved linearity. The linearity improvement is achieved through a combination of oversampling and mismatch shaping, which modulates the distortion energy out of band. Mismatch shaping can be realized in a traditional 1-bit/stage pipeline ADC, but the ADC's transfer characteristic properties limit its effectiveness at pushing the distortion out of band. These limitations can be alleviated by using a 1-bit/stage commutative feedback capacitor switching pipeline design. A test chip was fabricated in a 0.35-m CMOS process to demonstrate mismatch shaping. Experimental results obtained indicate that the spurious-free dynamic range improves by 8.5 dB to 76 dB when mismatch shaping is used at an oversampling ratio of 4 and a sampling rate of 61 MHz. The signal-to-noise and distortion ratio improves by 3 dB and the maximum integral nonlinearity decreases from 1.8 to 0.6 LSB at the 12-bit level.

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