Overview and Emerging Challenges in Wafer Thinning Process for Handheld Applications

Ganesh, V.P.; Lee, C.

doi:10.1109/iemt.2006.4456426

Cited by 10 publications

(3 citation statements)

References 21 publications

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“…Thinning of silicon chips is widely applied on wafer level, where the whole wafer is thinned down to a thickness of about 100 to 150 µm in a chemical or mechanical way [4]. As part of the Chip2Foil project, a single chip thinning process for small chip (1x1 mm 2 ) was developed and optimized.…”

Section: Chip Thinningmentioning

confidence: 99%

Towards reel-to-reel integration of ultra-thin chips to polymer foils

Tichem

Cauwe

Hajdarevic³

et al. 2012

2012 4th Electronic System-Integration Technology Conference

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The EU FP7 funded project Chip2Foil aims to realise a technology platform allowing a radically different implementation of the assembly process for ultra-thin chips (UTCs) to polymer foils. The process is based on redistribution of the tolerance budget, and consists of two major steps: self-assembly supported chip placement followed by an adaptive circuitry approach for realising the electrical interconnects. The concept accepts non-contact, low precision presentation of a UTC to the self-assembly force field, which brings the chip to a final position with moderate precision. Next, in an adaptive interconnection process the chip position is measured with respect to the circuitry on the foil and interconnects are created on an individual chip and IO basis. The main technology building blocks are described and the current performance is demonstrated, including chip thinning, fast UTC release from wafer tape, self-assembly supported chip placement using magnetic forces and adaptive electrical interconnection by laser scribing of a screen-printed silver patch.

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Section: Chip Thinningmentioning

confidence: 99%

Towards reel-to-reel integration of ultra-thin chips to polymer foils

Tichem

Cauwe

Hajdarevic³

et al. 2012

2012 4th Electronic System-Integration Technology Conference

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“…In this technology the wafer is thinned down to the desired thickness after the CMOS integration process [4]. However, it encounters some challenges concerning mechanical stability, very careful handling, and thickness non-uniformity across the wafer [5]. The Chipfilm TM technology is a novel concept aiming at overcoming the limitations of conventional chip backgrinding.…”

Section: Fabrication Of Ultra-thin Chips In Chipfilm Tm Technologymentioning

confidence: 99%

Self-aligned through silicon vias in ultra-thin chips for 3D-integration

Ferwana

Harendt

Letzkus

et al. 2012

2012 4th Electronic System-Integration Technology Conference

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Here, we present a new concept for enabling the formation of TSVs in ultra-thin chips fabricated by using the Chipfilm TM technology. In this technology a buried cavity is created underneath a Si-membrane which is attached to the substrate by vertical silicon anchors. By applying thermal oxidation, the side walls of these anchors and the narrow cavity are passivated. Due to the high selectivity of the silicon via etching process the oxidized silicon anchors and chip backside can be exploited for creating self-aligned TSVs. Accordingly, a seamless oxide isolation at the chip backside and inside the TSVs is provided.

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“…By using a combination of different wheels, i.e. rough and fine grinding, fast wafer thinning is achieved [6,7]. Furthermore cleaning allows for process simplification by allowing us to skip a CMP step intended for wafer planarization after grinding to remove or reduce grinding marks.…”

Section: Introductionmentioning

confidence: 99%