OWN: Optical and Wireless Network-on-Chip for Kilo-core Architectures

Sikder, Md. Ashif I.; Kodi, Avinash; Kennedy, Michael P.; Kaya, Savaş; Louri, Ahmed

doi:10.1109/hoti.2015.14

Cited by 22 publications

(15 citation statements)

References 20 publications

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“…has been therefore set in Table 3 as a main target. This value is of the same order of magnitude as the channel throughput considered in previous studies [4,6,8,17,35,43].…”

Section: Performance Assessment Of Optical Wireless Network-on-chipsupporting

confidence: 63%

Multi-Level Analysis of On-Chip Optical Wireless Links

et al. 2019

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Networks-on-chip are being regarded as a promising solution to meet the on-going requirement for higher and higher computation capacity. In view of future kilo-cores architectures, electrical wired connections are likely to become inefficient and alternative technologies are being widely investigated. Wireless communications on chip may be therefore leveraged to overcome the bottleneck of physical interconnections. This work deals with wireless networks-on-chip at optical frequencies, which can simplify the network layout and reduce the communication latency, easing the antenna on-chip integration process at the same time. On the other end, optical wireless communication on-chip can be limited by the heavy propagation losses and the possible cross-link interference. Assessment of the optical wireless network in terms of bit error probability and maximum communication range is here investigated through a multi-level approach. Manifold aspects, concurring to the final system performance, are simultaneously taken into account, like the antenna radiation properties, the data-rate of the core-to core communication, the geometrical and electromagnetic layout of the chip and the noise and interference level. Simulations results suggest that communication up to some hundreds of μm can be pursued provided that the antenna design and/or the target data-rate are carefully tailored to the actual layout of the chip.

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“…has been therefore set in Table 3 as a main target. This value is of the same order of magnitude as the channel throughput considered in previous studies [4,6,8,17,35,43].…”

Section: Performance Assessment Of Optical Wireless Network-on-chipsupporting

confidence: 63%

Multi-Level Analysis of On-Chip Optical Wireless Links

et al. 2019

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“…Wireless interconnects reduce the hop count between the optically connected clusters, leading to improved performance and more efficient utilization of the finite wireless bandwidth. Our previous results indicate that OWN architecture consumes 30.36% less energy, and improves throughput by 8% over wireless-alone architectures and obtains 35.5% less area than optical-alone architectures [18].…”

Section: Network-on-chip Architecturementioning

confidence: 94%

“…The antenna structures proposed are for a novel Optical-Wireless NoC (OWN) architecture for kilo-core computing that utilizes both optical and wireless interconnects [18]. Wireless interconnects reduce the hop count between the optically connected clusters, leading to improved performance and more efficient utilization of the finite wireless bandwidth.…”

Section: Network-on-chip Architecturementioning

confidence: 99%

Monopoles Loaded With 3-D-Printed Dielectrics for Future Wireless Intrachip Communications

Kodi

Kaya

et al. 2017

IEEE Trans. Antennas Propagat.

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We propose a novel antenna design enabled by 3-D printing technology for future wireless intra-chip interconnects aiming at applications of multicore architectures and system-on-chips (SoCs). In our proposed design we use vertical quarter-wavelength monopoles at 160 GHz on a ground plane to avoid low antenna radiation efficiency caused by the silicon substrate. The monopoles are surrounded by a specially-designed dielectric property distribution. This additional degree of freedom in design enabled by 3-D printing technology is used to tailor the electromagnetic wave propagation. As a result, the desired wireless link gain is enhanced and the undesired spatial crosstalk is reduced. Simulation results show that the proposed dielectric loading approach improves the desired link gain by 8-15 dB and reduces the crosstalk by 9-23 dB from 155 GHz to 165 GHz. As a proof-of-concept, a 60 GHz prototype is designed, fabricated and characterized. Our measurement results match the simulation results and demonstrate 10-18 dB improvement of the desired link gain and 10-30 dB reduction in the crosstalk from 55 GHz to 61 GHz. The demonstrated transmission loss of the desired link at a distance of 17 mm is only 15 dB, which is over 10 dB better than the previously reported work. Index Terms-antennas; electromagnetic propagation; interconnect; intra-chip communication; multiprocessor interconnection; network on chip; 3-D printing I. INTRODUCTION HE continuing reduction in CMOS feature size has resulted in sub-10 nm (Intel just announced a 7-nm fab in Phoenix, Arizona [1]) which will allow integration of kilo-core (1000

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“…Note, however, that the principles of ORTHONOC can be applied over any topology and interconnect technology. For instance, longer term designs can employ a nanophotonic network capable of serving unicast and local traffic with outstanding power efficiency and bandwidth density [4], [35].…”

Section: Overview Of Orthonocmentioning

confidence: 99%

“…Also, the broadcast scalability of the approach is highly questionable due to laser power scaling issues [16]. Instead, existing hybrid proposals overlay a nanophotonic bus or crossbar over a conventional mesh [51], or over a wireless network [35] to leverage the unique properties of optics. Note, in any case, that the design principles of ORTHONOC can be applied to any combination of interconnect technologies.…”

Section: Related Workmentioning

confidence: 99%

OrthoNoC: A Broadcast-Oriented Dual-Plane Wireless Network-on-Chip Architecture

Abadal

Torrellas

Alarcón

et al. 2018

IEEE Trans. Parallel Distrib. Syst.

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Abstract-On-chip communication remains as a key research issue at the gates of the manycore era. In response to this, novel interconnect technologies have opened the door to new Network-on-Chip (NoC) solutions towards greater scalability and architectural flexibility. Particularly, wireless on-chip communication has garnered considerable attention due to its inherent broadcast capabilities, low latency, and system-level simplicity. This work presents ORTHONOC, a wired-wireless architecture that differs from existing proposals in that both network planes are decoupled and driven by traffic steering policies enforced at the network interfaces. With these and other design decisions, ORTHONOC seeks to emphasize the ordered broadcast advantage offered by the wireless technology. The performance and cost of ORTHONOC are first explored using synthetic traffic, showing substantial improvements with respect to other wired-wireless designs with a similar number of antennas. Then, the applicability of ORTHONOC in the multiprocessor scenario is demonstrated through the evaluation of a simple architecture that implements fast synchronization via ordered broadcast transmissions. Simulations reveal significant execution time speedups and communication energy savings for 64-threaded benchmarks, proving that the value of ORTHONOC goes beyond simply improving the performance of the on-chip interconnect.

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OWN: Optical and Wireless Network-on-Chip for Kilo-core Architectures

Cited by 22 publications

References 20 publications

Multi-Level Analysis of On-Chip Optical Wireless Links

Multi-Level Analysis of On-Chip Optical Wireless Links

Monopoles Loaded With 3-D-Printed Dielectrics for Future Wireless Intrachip Communications

OrthoNoC: A Broadcast-Oriented Dual-Plane Wireless Network-on-Chip Architecture

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