Oxidation of Si and GaAs in air at room temperature

Lukeš, F.

doi:10.1016/0039-6028(72)90025-8

Cited by 172 publications

(58 citation statements)

References 4 publications

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“…In the control samples, a native oxide of ~30 nm in thickness was uniformly distributed over the surfaces of the sample, including the notch. While thick compared to the native oxide that will typically develop on single crystal silicon at room temperature [30][31][32][33], the presence of heavy phosphorous doping and elevated temperature exposure during drying of the film created a significantly thicker reaction layer. 30-nm thick native oxide layers were also present on the tested fatigue sample, except in the vicinity of the notch where the oxide layer was significantly thicker.…”

Section: Fatigue Fracturesmentioning

confidence: 99%

A reaction-layer mechanism for the delayed failure of micron-scale polycrystalline silicon structural films subjected to high-cycle fatigue loading

2002

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Abstract-A study has been made of high-cycle fatigue in 2-µm thick structural films of n + -type, polycrystalline silicon for MEMS applications. Using an "on-chip" test structure resonating at ~40 kHz, such thin-film polysilicon is shown to display "metal-like" stress-life fatigue behavior in room air environments, with failures occurring after lives in excess of 10 11 cycles at stresses as low as half the fracture strength. Through in-situ monitoring of the natural frequency to evaluate the damage evolution by notch-root oxidation and cracking, and using transmission electron microscopy to image such damage, it is concluded that the mechanism of thin-film silicon fatigue involves sequential oxidation and environmentallyassisted cracking in the native SiO 2 layer. This moisture-induced "reaction-layer fatigue" mechanism can also occur in bulk silicon but it is only significant in thin films where the critical crack size for catastrophic failure can be reached by a crack growing within the oxide layer. The susceptibility of thin-film silicon to fatigue failure is shown to be suppressed by the use of alkene-based self-assembled monolayer coatings that prevent the formation of the native oxide.

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Section: Fatigue Fracturesmentioning

confidence: 99%

A reaction-layer mechanism for the delayed failure of micron-scale polycrystalline silicon structural films subjected to high-cycle fatigue loading

2002

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“…The data are well-fitted by a logarithmic function, in accord with experiments on the time dependence of the room temperature growth of thin native oxide films on bulk Si surfaces. 13 The emission energies of the smallest diameter nanocrystals clearly cannot be constrained to the calculated curve of Fig. 3(a), because the PL redshifted as the oxidation time increased (and presumably as particle size decreased).…”

mentioning

confidence: 99%

Size-dependent oxygen-related electronic states in silicon nanocrystals

Biteen

Lewis

Atwater

et al. 2004

Applied Physics Letters

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Silicon nanocrystals embedded in SiO 2 were isolated with a selective etching procedure, and the isolated nanocrystals' excitonic emission energy was studied during controlled oxidation. Nanocrystals having initial diameters, d 0 , of ϳ2.9-3.4 nm showed a photoluminescence ͑PL͒ blueshift upon oxidatively induced size reduction, as expected from models of quantum confinement. Oxidation of smaller Si nanocrystals ͑d 0 ϳ 2.5-2.8 nm͒ also initially resulted in a PL blueshift, but a redshift in the PL was then observed after growth of ϳ0. 2 Detailed assessments of the relationship between Si nanocrystal size and band gap using self-consistent tight binding 3 and Quantum Monte Carlo ͑QMC͒ 4 methods predict a continuous increase in band gap with decreasing diameter down to diameters less than 1 nm. Experimental measurements have confirmed that the excitonic emission energy of Si nanocrystals increases as the nanocrystal size decreases, but the increase is smaller than that expected theoretically. 3,5,6 This discrepancy suggests the presence of excitonic recombination through a localized electronic state whose energy level lies within the band gap of the smaller Si nanocrystals.Si nanocrystals are typically embedded in silicon dioxide or surrounded by a native oxide layer, and theoretical models suggest that oxygen-related states at the nanocrystal surface can produce intragap energy levels.3,4 Wolkin and coworkers evaluated theoretically the effect of a surface silicon-oxygen double bond ͑Si= O͒ on the electronic band structure of a Si nanocyrstal.3 Their semiempirical computations predicted that the energy difference between the conduction and valence bands would increase roughly according to r −2 , but their calculations also predicted that, for nanocrystals with d Ͻ ϳ 3 nm, the Si= O bond should produce interface states that lie within the band gap. Puzder et al. used QMC calculations for small nanocrystals and interpolated to the bulk band gap with trends from density functional theory to confirm the semiempirical results. 4 More recently, reports of nonlinear optical effects in Si nanocrystal systems have invoked three-or four-level models that require, along with the Si band edges, the presence of deep-lying surface states. 7,8 To test these interface-related excitonic recombination models experimentally, we have used PL spectroscopy to measure the exciton recombination energy of Si nanocrystals in a well-controlled size range, d ϳ 2.5-3.4 nm, with and without passivation by an oxygen environment.Ensembles of Si nanocrystals were produced by implantation of 15 keV Si + ions to a fluence of 1.3ϫ 10 16 cm −2 into 15-nm-thick silicon dioxide films that were grown by thermal oxidation of lightly p-doped Si͑100͒. According to SRIM,9 a Monte Carlo simulation program, such implantations lead to a Gaussian depth distribution of silicon in the SiO 2 matrix and produce a peak excess Si concentration of 15% at a depth of 10 nm. The implanted samples were annealed at 1100°C for 5 min in Ar. Transmission electron microscopy r...

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“…2(a) reflects the self-limiting nature of the oxidation process; once the oxide thickness is thick enough, the diffusion rate of oxidizing species is sharply curtailed. The data between 50 to 500 s follows Lukeš' rate law for GaAs oxidation [14]: d=A+B·log(t+t o ) with fitting parameters A =0 nm, B =0.44 nm/dec and t o = −37 s. The negative t o value reflects the incubation time of the O 2 plasma oxidation process. Because of this, the fitting applies for t + t o > 0.…”

Section: Methodsmentioning

confidence: 98%

A Novel Digital Etch Technique for Deeply Scaled III-V MOSFETs

Lin

Zhao

Antoniadis

et al. 2014

IEEE Electron Device Lett.

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Abstract-We demonstrate a new digital etch technique for controllably thinning III-V semiconductor heterostructures with sub-1-nm resolution. This is a two-step process consisting of lowpower O 2 plasma oxidation, followed by diluted H 2 SO 4 rinse for selective oxide removal. This approach can etch a combination of InP, InGaAs, and InAlAs in a precise and nonselective manner. We have also developed a method to determine the etch rate per cycle, and to control the etch depth in actual device structures. For InP, the etch rate is ∼0.9 nm/cycle. We illustrate the new process by fabricating L g = 60-nm selfaligned buried-channel InGaAs MOSFETs. These devices feature a composite gate dielectric consisting of 1-nm InP and 2-nm HfO 2 for an overall sub-1-nm effective oxide thickness. A typical device shows a peak transconductance of 1.53 mS/µm (V ds = 0.5 V), subthreshold swing of 89 mV/decade, and 102 mV/decade at V ds = 0.05 and 0.5 V, respectively, and ON current of 326 µA/µm at I OFF = 100 nA/µm and V dd = 0.5 V.

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Oxidation of Si and GaAs in air at room temperature

Cited by 172 publications

References 4 publications

A reaction-layer mechanism for the delayed failure of micron-scale polycrystalline silicon structural films subjected to high-cycle fatigue loading

A reaction-layer mechanism for the delayed failure of micron-scale polycrystalline silicon structural films subjected to high-cycle fatigue loading

Size-dependent oxygen-related electronic states in silicon nanocrystals

A Novel Digital Etch Technique for Deeply Scaled III-V MOSFETs

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