Oxidation of Silicon Nanopillars

Abstract

Systematic investigation of dry oxidation of sub-100 nm diameter Si nanopillars (NPs) of various diameters under varying conditions reveals that at 900 °C, the oxidation involves a deep self-limiting oxidation step where the oxidation nearly stops, and the consumed Si thickness (y) exhibits a first-order-reactionlike relation, y = a 1 × (1 − exp (−b 1 × t)), under an oxidation time t. At 1000 °C, the high oxidation rate with a slight self-limiting step is observed and small NPs could be entirely oxidized. In this case, the relation changes to y = a 2 × t ^b2 . The above equations are confirmed to be applicable for all reported Si NPs and nanowires. Importantly, the relation y ^2 ∝ t that is widely used for Si oxidation in traditional theories can only express oxidation of planar, concave, and large convex surfaces but not for Si NPs and nanowires. Since the oxide around Si NPs is found to grow radially and has a lower density compared to that on the planar surfaces oxidized under the same conditions, oxidation-induced stress in Si and/ or tensile stress in oxides is considered to dominate the oxidation of Si NPs via affecting the reaction rate constant instead of oxidant diffusion inhibition. This study contributes to a deeper understanding of the oxidation of nanostructured Si, as well as nanostructured metals. It also supports the precise design/fabrication of Si NP-based sub-10 nm devices such as gate-all-around transistors, optoelectronic devices, and biosensors.

CMOS-Compatible Wafer-Level Double-layer Silicon Nanograss through Reactive Ion Etching for Applications in Optics

“…This barrier effect can develop silicon nanopillar arrays (devoid of nanograss) by introducing sacrificial structures around the silicon nanopillars (Figure S6). The sacrificial structures can be removed by other means (isostatic dry etching, oxidation combined pickling, 40 or ultrasonic cleaning 38 ).…”

Fabrication of high-aspect-ratio SiO2 nanopillars by Si thermal oxidation for metalenses in the visible region

“…One of the reasons for the difference between the expected value of 833 μm and the measured value of 1000 μm may be that the thickness of the device Si layer used in the design was not accurate resulting in a nonideal focusing. It is also possible that Si, which has a higher refractive index than SiO 2 , is insufficiently oxidized and remains in the center of the pillars, 60,65) increasing the effective refractive index of the pillars. If the pillar height is a constant in Eq.…”

Formation of Si nanopillars through partial sacrificing in super passivation reactive ion etching

“…Specially, the VGAA MOSFET is a crucial component in threedimensional (3D) integrated circuits (ICs) [3][4][5][6][7][8]. Si nanopillars, serving as a promising channel for the VGAA MOSFET, should have cylindrical shape, precise position, uniform arrays and smooth bottom surface [9][10][11][12][13]. Si nanopillars are primarily fabricated through wet and dry etching methods [14][15][16][17][18].…”