2019
DOI: 10.1002/sdtp.13152
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P‐3: A Study on the Hot Carrier Effect in InGaZnO Thin Film Transistors

Abstract: This study provides the most plausible origin of the drain current drop (DCD) phenomenon by hot carrier effect in InGaZnO thin film transistors (IGZO-TFTs). The degraded performance of IGZO-TFTs after the DCD phenomenon was related to the charge trapping and modification of the electronic structure by collision of an IGZO matrix with hot carriers. Author KeywordsIGZO-TFTs; Hot carrier effect; Drain current drop phenomenon; Electronic structure; band edge state.

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Cited by 23 publications
(10 citation statements)
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“…The reliability of amorphous oxide semiconductor thinfilm transistors (AOS-TFTs) is vital for high-definition displays and functional electronic devices. However, drain current drop (DCD) degradation has been commonly observed in the output characteristics of TFTs with channel lengths of L<10 μm [1,2]. Here, we show that DCD is a reversible process that is closely related to reduced metaloxygen bonds and is most likely caused by destruction induced by hot electrons.…”
Section: Introductionmentioning
confidence: 70%
“…The reliability of amorphous oxide semiconductor thinfilm transistors (AOS-TFTs) is vital for high-definition displays and functional electronic devices. However, drain current drop (DCD) degradation has been commonly observed in the output characteristics of TFTs with channel lengths of L<10 μm [1,2]. Here, we show that DCD is a reversible process that is closely related to reduced metaloxygen bonds and is most likely caused by destruction induced by hot electrons.…”
Section: Introductionmentioning
confidence: 70%
“…5(c)). Therefore, the rapid decrease in current at low VGS is explained by hot carrier generation by impact ionization [9] or Zn-O bond breaking [10] and local VT increase due to trapping near the drain, independent of dopant diffusion. In other words, it can be interpreted that defect creation occurs by hot electrons near the drain where the field is concentrated and that the electrons are trapped and locally decrease.…”
Section: Vds-sweepmentioning
confidence: 99%
“…In order for oxide TFTs to replace the Si CMOS backplane, the facile integration process of submicron scale devices should be developed on the glass substrate. Furthermore, short‐channel effects such as drain‐induced barrier lowering (DIBL), hot carrier effects (HCE), and inappropriate leakage current are major concerns 17–19 . Non‐planar architectures such as three‐dimensional (3D)‐vertical, recess channel, or FinFET structures can provide solutions to these fundamental issues.…”
Section: Introductionmentioning
confidence: 99%