Abstract— A novel gate‐driver circuit using amorphous‐silicon (a‐Si) TFTs has been developed. The circuit has a shared‐node dual pull‐down AC (SDAC) structure with a common‐node controller for two neighboring stages, resulting in a reduced number of TFTs. The overlapped clock signals widen the temperature range for stable operation due to the extended charging time of the inner nodes of the circuit. The accelerated lifetime was found to be over 1000 hours at 60°C with good bias‐temperature‐stress (BTS) characteristics. Accordingly, the a‐Si gate‐driver circuit was successfully integrated into a 14.1‐in. XGA (1024 × RGB × 768) TFT‐LCD panel having a single bank form.

A novel integrated gate driver with a simple logic circuit (SLC) using 5 a-Si TFTs has been developed. The noise voltage owing to clock coupling is eliminated effectively with an overlapped clock controlled transistor. The SLC gate driver, successfully integrated in 14.1-in. XGA TFT-LCD's, shows marked stability despite the extremely simple structure.

The characteristic feature of an optimum design of a-Si gate driver circuits and its scaling properties are presented. The delay time of the output pulse of gate driver circuits with different layout characteristics was analyzed by a distributed-load modeling. The effect of TFT properties, clock phase and the output load on the optimum condition is given. Finally, scaling has been found to give apparent power law dependence on the circuit area, signifying higher performance of the circuits with smaller area.

Tuning the process pressure at the deposition of the passivation layers has been suggested in the way of controlling the threshold voltage of a-IGZO TFTs, making it possible to employ gate driver integration. It has showed that V th linearly changes with the pressure (ΔV th /ΔPressure~3.5V/100Pa). A 3.2 inch WVGA AMLCD with integrated gate driver circuits were successfully demonstrated using the enhancement mode BCE type bottom gate a-IGZO TFTs.

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